Multi-valued Arbiters for quality enhancement of PUF responses on FPGA implementation

Zalivaka, Siarhei S.; Puchkov, A. V.; Klybik, Vladimir P.; Ivaniuk, Alexander A.; Chang, Chip-Hong

doi:10.1109/aspdac.2016.7428066

Cited by 30 publications

(21 citation statements)

References 10 publications

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“…It was confirmed by our earlier experiments [110] that FPGA implementation of classical 128-stage A-PUF has average reliability of only 0.577. This is far from the acceptable BER requirement of 10 −6 based on the standard of BER [114] required for a 128-bit key generator.…”

Section: Reliability Testsupporting

confidence: 67%

“…return True 39: end procedure 65. Some unstable challenges can be corrected by identifying and recoding the metastable states using the method in [110]. For example, the response quadruples {0, 0, X, 1} and {0, 0, 1, X} can be easily corrected to {0, 0, 1, 1} and the response quadruples {X, 1, 0, 0} and {1, X, 0, 0} can be easily corrected to {1, 1, 0, 0}.…”

Section: Reliability Enhancement Algorithmmentioning

confidence: 99%

“…Because it has 45.9% of zeros and 54.1% of ones, it is not able to pass the frequency based tests (Frequency, Frequency block, Runs, The longest run and Cumulative sums). This 1-skew problem can be mitigated by detecting and recoding the metastability states into stable logic 0 states [110]. Alternatively, the persistently stable response set of A-PUF can be post-processed by some functions like Von Neumann corrector, Linear Feedback…”

Section: Randomness Testmentioning

confidence: 99%

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Arbiter PUF based FPGA chip identification and authentication methods with enhanced reliability and modeling attack resistance

Zalivaka¹

Self Cite

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I would like to express my gratitude to my supervisors for constant support and reasonable criticism of my research efforts. I doubt, that I could finish my Ph. D. study without their inspiration and passion about the research area I have chosen. First, I would like to thank Associate Professor Chang Chip-Hong, who offered me a research scholarship in Nanyang Technological University (NTU). It has been a great experience to work in world-class research group which is recognized all over the world. Prof. Chang has given many insights on critical thinking via research paper reviewing. His experience and expertise in the research influenced great improvement in my research and experimental design skills, paper writing and general knowledge. Then, I would like to thank Alexander A. Ivaniuk, Professor of

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Section: Reliability Testsupporting

confidence: 67%

Section: Reliability Enhancement Algorithmmentioning

confidence: 99%

Section: Randomness Testmentioning

confidence: 99%

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Arbiter PUF based FPGA chip identification and authentication methods with enhanced reliability and modeling attack resistance

Zalivaka¹

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“…Properties that designers should meet when designing ML resistant strong PUF designs are suggested in [31], however a practical instantiation remains unsolved. A multi-arbiter scheme is proposed in [32], based on the insertion of either a four-flip-flop or SR latch arbiter after each stage in the configurable paths, thus improving the uniqueness and reliability of the APUF design. However, the resistance of this approach to modelling attacks has not been reported.…”

Section: Reviewmentioning

confidence: 99%

A Flip-Flop Based Arbiter Physical Unclonable Function (APUF) Design with High Entropy and Uniqueness for FPGA Implementation

Liu

Cui

et al. 2021

IEEE Trans. Emerg. Topics Comput.

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A PUF is a physical security primitive that allows to extract intrinsic digital identifiers from electronic devices. It is a promising candidate to improve security in lightweight devices targeted at IoT applications due to its low cost nature. The Arbiter PUF or APUF has been widely studied in the technical literature. However it often suffers from disadvantages such as poor uniqueness and reliability, particularly when implemented on FPGAs due to physical layout restrictions. To address these problems, a new design known as FF-APUF has been proposed; it offers a compact architecture, combined with good uniqueness and reliability properties, and is well suited to FPGA implementation. Many PUF designs have been shown to be vulnerable to machine learning (ML) based modelling attacks. In this paper, initial tests show that to attack the FF-APUF design requires more effort for the adversary than a conventional APUF design. A comprehensive analysis of the experimental results for the FF-APUF design is presented to show this outcome. An improved APUF design with a balanced routing, and the proposed FF-APUF design are both implemented on an Xilinx Artix-7 FPGA at 28 nm technology. The empirical min-entropy of the FF-APUF design across different devices is shown to be more than twice that of the conventional APUF design.

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“…Metastability in cross-coupled paths have been exploited to design PUF with SR latch [3]- [5] and Ring Oscillator (RO) [6]. Although latch-based PUF designs offer unique signatures to ICs, they suffer from signal skew and delay imbalance in signal routing paths and Error Correction Code (ECC) circuitry is commonly employed to post-process the instable PUF responses [7]. On the contrary, RO-PUF in [6] incurs significant area overhead that includes a counter, an accumulator, and a shift register.…”

Section: Introductionmentioning

confidence: 99%

An SR Flip-Flop based Physical Unclonable Functions for Hardware Security

Challa

Islam

Katkoori

2019

2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)

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Physical Unclonable Functions (PUFs) have emerged as a promising solution to identify and authenticate Integrated Circuits (ICs). In this paper, we propose a novel NAND-based Set-Reset (SR) Flip-flop (FF) PUF design for security enclosures of the area-and power-constrained Internet-of-Things (IoT) edge node. Such SR-FF based PUF is constructed during a unique race condition that is (normally) avoided due to inconsistency. We have shown, when both inputs (S and R) are logic high ('1') and followed by logic zero ('0'), the outputs Q and Q can settle down to either 0 or 1 or vice-versa depending on statistical delay variations in cross-coupled paths. We incorporate the process variations during SPICE-level simulations to leverage the capability of SR-FF in generating the unique identifier of an IC. Experimental results for 90nm, 45nm, and 32nm process nodes show the robustness of SR-FF PUF responses in terms of uniqueness, randomness, uniformity, and bit(s) biases. Furthermore, we perform physical synthesis to evaluate the applicability of SR FF PUF on five designs from OpenCores in three design corners. The estimated overhead for power, timing, and area in three design corners are negligible.

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Multi-valued Arbiters for quality enhancement of PUF responses on FPGA implementation

Cited by 30 publications

References 10 publications

Arbiter PUF based FPGA chip identification and authentication methods with enhanced reliability and modeling attack resistance

Arbiter PUF based FPGA chip identification and authentication methods with enhanced reliability and modeling attack resistance

A Flip-Flop Based Arbiter Physical Unclonable Function (APUF) Design with High Entropy and Uniqueness for FPGA Implementation

An SR Flip-Flop based Physical Unclonable Functions for Hardware Security

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