Multi‐valued logic design methodology with double negative differential resistance transistors

Abstract

Multi-valued logic (MVL) is one of the promising alternatives of binary logic since it has a high-logic density, which brings a vision of simpler circuit structure. Based on a novel concept as double negative differential resistance field effect transistor and its analytic description, a design methodology utilising the mechanism of monostable-to-multistable transition logic element (MMLE) for MVL is proposed in this study. The basic ternary logic gates are designed as a complete logic set, and a compact ternary four-input full adder is constructed as an example of function circuits. Comparing with binary circuit and ternary circuit based on conventional design, the circuit shows advantage in device cost and other properties. The results verify that this MMLE design methodology has a good information load ability, which will have a brilliant prospect in MVL circuits.

Antiambipolar Transistor: A Newcomer for Future Flexible Electronics

“…Graphene can also be used as a constituent component of an MVL. Ji et al performed a theoretical simulation and predicted that a double NDR transistor can be realized by designing graphene channel shapes . Park and co‐workers observed a photoinduced NDR in the graphene/WSe 2 heterointerface and developed a light‐triggered ternary inverter.…”

Influence of Parasitic Effects in Negative Differential Resistance Characteristics of Resonant Tunneling

“…The room temperature I-V measurement of double barrier resonant tunneling (DBRT) structure has been also proposed before 1974 [6]. The tunneling mechanisms of traditional RTEC structures have been also reported in literatures previously, which mechanism are different from the tunneling mechanism of the traditional RTPD structure, and the traditional RTEC structures have been also successfully applied in MVLL systems [2,10,11]. Even so, a new RTEC physical structure with reactance elements will be proposed and explored in this research.…”

“…Because the majority carriers occupy the quantum well of RTPD structure, the life time of majority carrier is existed which is denoted by τ 1 . The life time (τ 1 ) can be calculated by using uncertainty principle, as shown in Equation (1a) where ∆E n is the full width of half magnitude (FWHM) of nth binding state in quantum well of RPTD structure [2]. However, the time constant (τ 2 ) of RTEC unit was derived from transient response theory in transient circuit, as presented in Equation (1b) [1].…”

“…Besides, due to the vigorous development of high-frequency communication and extensive applications of many communication elements including radio frequency identify devices (RFIDs), microwave frequency communications (MFCs), and optical fiber communications (OFCs), RTEC unit will also has more opportunity in integration with other electronic devices. Therefore, well-defined RTEC could be suitably applied in many microwave frequency devices (MFDs) and multiple values logical level memory devices (MVLL-MDs), which the operation frequency and the logical values could be respectively more than 700 GHz and reach as three logical levels [1][2][3]. In this research, therefore, the exploration of parasitic elements in RTEC unit was supported to enhance the function of RTEC units in the applications of MFDs and MVLL-MDs.…”

“…Additionally, the well-designed RTEC unit can be also applied in other digital and analog elements including NAND/NOR logical gates, A/D or D/A convertors, multiple value counters, frequency dividers, multiple value logical gates, full adders, decoders, exclusive OR gates, invertors, 2 of 13 high-frequency oscillators, multiple MVLL-MDs, multiple frequency circuits, oscillators, and voltage regulators by suitable selection of various design-thinking and different fabrication techniques in RTEC unit. Especially, the design of a MVLL system accompanied the RTEC unit could be developed as a faster and higher-capacity MDs which could supersede to the prevalent DRAM devices [1,2].…”