Multichip Embedding Technology Using Fine-Pitch Cu–Cu Interconnections

Khan, Sadia; Choudhury, Arnab; Kumbhat, Nitesh; Pulugurtha, Markondeya Raj; Meyer-Berg, Georg; Tummala, Rao

doi:10.1109/tcpmt.2012.2235528

Cited by 12 publications

(4 citation statements)

References 13 publications

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“…While many solutions are available for embedding components in rigid substrates [11][12][13], recently a trend toward flexible systems is emerging [14][15][16]. Chip embedding into a foil substrate can be either arranged directly or via a foil interposer.…”

Section: Assembly and Embedding Of Thin Chips In Foilmentioning

confidence: 99%

Hybrid Systems in Foil (HySiF) exploiting ultra-thin flexible chips

Harendt

Kostelnik

Kugler

et al. 2015

Solid-State Electronics

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Section: Assembly and Embedding Of Thin Chips In Foilmentioning

confidence: 99%

Hybrid Systems in Foil (HySiF) exploiting ultra-thin flexible chips

Harendt

Kostelnik

Kugler

et al. 2015

Solid-State Electronics

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“…Conventional approaches to chip integration such as wire bonding, solder, epoxy, and cold welding (Au-Au joints, etc.) or brazing face limitations of messiness, accuracy, temperature, signal loss, and process time, motivate the search for novel technologies for heterogeneous integration [1][2][3][4][5][6][7][8][9][10][11]. This work examines the potential for microfabricated interlocking structures to achieve manufacturing integration of heterogeneous components as seen in Fig.…”

Section: Introductionmentioning

confidence: 99%

Design of Microfabricated Mechanically Interlocking Metamaterials for Reworkable Heterogeneous Integration

Garcia

Wakumoto

Brown

2021

Journal of Electronic Packaging

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Next–generation interconnects utilizing mechanically interlocking structures enable permanent and reworkable joints between microelectronic devices. Mechanical metamaterials, specifically dry adhesives, are an active area of research which allows for the joining of objects without traditional fasteners or adhesives, and in the case of chip integration, without solder. This paper focuses on reworkable joints that enable chips to be removed from their substrates to support reusable device prototyping and packaging, creating the possibility for eventual pick-and-place mechanical bonding of chips with no additional bonding steps required. Analytical models are presented and are verified through Finite Element Analysis (FEA) assuming pure elastic behavior. Sliding contact conditions in FEA simplify consideration of several design variations but contribute ~10% uncertainty relative to experiment, analysis, and point-loaded FEA. Two designs are presented; arrays of flat cantilevers have a bond strength of 6.3 kPa, and non-flat cantilevers have a strength of 29 kPa. Interlocking designs present self-aligning in-plane forces that emerge from translational perturbation from perfect alignment. Stresses exceeding the material yield stress during adhesion operations present a greater concern for repeatable operation of compliant interlocking joints and will require further study quantifying and accommodating plastic deformation. Designs joining a rigid array with a complementary compliant cantilever array preserve the condition of reworkability for the surface presenting the rigid array. Eventual realization of interconnect technology based on this study will provide a great improvement of functionality and adaptability in heterogeneous integration and microdevice packaging.

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“…According to a previous report on bumping interconnect technology roadmap (Yole Développement), fine-pitch interconnections for flip-chip technology are projected to decrease to 30 µm by the year 2016. 10) Although fine-pitch interconnections with a connection pitch of less than 30 µm have been introduced recently, [11][12][13][14][15][16][17][18][19][20][21] post-bond misalignment still remains an issue in these works, resulting in a high risk of bridging between neighboring connections, and the limitation in interconnection pitches. On the other hand, in spite of the use of critical alignment procedures and complex actuation systems, it is still a challenge to increase the yield of these bonding processes.…”

Section: Introductionmentioning

confidence: 99%

15-µm-pitch Cu/Au interconnections relied on self-aligned low-temperature thermosonic flip-chip bonding technique for advanced chip stacking applications

Thanh

Kato

Watanabe

et al. 2014

Jpn. J. Appl. Phys.

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In this paper, we report the development of reliable fine-pitch micro bump interconnections that used a high-precision room-temperature bonding approach. The accuracy of the bonding process is improved by modifying conventional bump/planar-bonding-pad interconnections to form self-aligned micro bumps/truncated inverted pyramid (TIP) bonding pads, i.e., misalignment self-correction elements (MSCEs). Thermosonic flip-chip bonding (FCB) is utilized to form reliable bonds between these MSCEs at acceptable low temperatures. By applying the proposed bonding approach, the demonstration of fine-pitch Cu bump to Au bonding pad interconnects chip stacking has been realized. Microstructure analyses reveal that 15-µm-pitch micro bump joints are fabricated at room temperature.

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Multichip Embedding Technology Using Fine-Pitch Cu–Cu Interconnections

Cited by 12 publications

References 13 publications

Hybrid Systems in Foil (HySiF) exploiting ultra-thin flexible chips

Hybrid Systems in Foil (HySiF) exploiting ultra-thin flexible chips

Design of Microfabricated Mechanically Interlocking Metamaterials for Reworkable Heterogeneous Integration

15-µm-pitch Cu/Au interconnections relied on self-aligned low-temperature thermosonic flip-chip bonding technique for advanced chip stacking applications

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