Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset

Martin, Milo M. K.; Sorin, Daniel J.; Beckmann, Bradford M.; Marty, Michael R.; Xu, Min; Alameldeen, Alaa R.; Moore, Kevin Ezra; Hill, Mark D.; Wood, David А.

doi:10.1145/1105734.1105747

Cited by 1,275 publications

(580 citation statements)

References 19 publications

Supporting

Mentioning

563

Contrasting

Unclassified

Order By: Relevance

“…We chose RSIM as performance simulator instead of a full-system simulator such as GEMS/Simics [16] or M5 [4] for several reasons. First, RSIM models the memory hierarchy and the interconnection network in more detail.…”

Section: Related Workmentioning

confidence: 99%

An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures

Flores¹,

Aragón²,

Acacio³

2008

J Supercomput

View full text Add to dashboard Cite

Continuous improvements in integration scale have made possible the inclusion of several processor cores on the same chip. Such designs have been named chip-multiprocessors (or CMPs) and constitute a good alternative to traditional monolithic designs for several reasons, among others, better levels of performance, scalability, and performance/energy ratio. On the other hand, higher clock frequencies and increasing number of transistors available on a single chip have revealed energy consumption as a critical design issue in current and future microarchitectures. In these architectures, the design of the on-chip interconnection network has proven to have significant impact on overall system performance and energy consumption, and that the wires used in such interconnect can be designed with varying latency, bandwidth, and power characteristics.In this work, we present a detailed characterization of the energy-efficiency of a CMP for parallel scientific applications using Sim-PowerCMP, a detailed architectural-level power-performance simulation tool for CMP architectures that integrates several well-known contemporary simulators (RSIM, Hot Leakage and Orion) into a single framework that allows precise analysis and optimization of power dissipation (both dynamic and static) taking into account performance. In this characterization, we pay special attention to the energy consumed on the interconnection network. Results for an 8-and 16-core CMP show that the most power consuming messages are the replies that carry data (almost 70% on average of the total energy consumed in the interconnect) although they represent 30% of the total number of messages. Furthermore, we show that using on-chip wires with varying latency, bandwidth, and energy characteristics can reduce the energy dissipated by the links of the interconnection network about 65% with an average impact of 10% in the execution time.

show abstract

Section: Related Workmentioning

confidence: 99%

An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures

Flores¹,

Aragón²,

Acacio³

2008

J Supercomput

View full text Add to dashboard Cite

show abstract

“…We simulate a 16-core CMP system with an open source multiprocessor simulator GEMS [12], which is developed by Wisconsin Multifacet project and built on the Virtutech Simics [13] full-system functional execution-driven simulator. GEMS simulator adds timing information of memory hierarchy and interconnection on simics.…”

Section: Experiments Environment and Resultsmentioning

confidence: 99%

Exploit Temporal Locality of Shared Data in SRC Enabled CMP

Wang

et al. 2007

Lecture Notes in Computer Science

View full text Add to dashboard Cite

Abstract. By run-time characteristic analysis of parallel workloads, we found that a majority of shared data accesses of parallel workload has temporal locality. Based on this characteristic, we present a sharing relation cache (SRC for short) based CMP architecture, saving recently used sharing relations to provide destination set information for following cache-to-cache miss requests. Token-SRC protocol integrates SRC into token protocol,reducing network traffic of token protocol.Simulations using SPLASH-2 benchmarks show that, a 16-core CMP system with token-SRC achieved average 15% network traffic reduction of that with token protocol.

show abstract

“…We use a full-system execution-driven simulation based on the Wisconsin GEMS toolset [7], in conjunction with Virtutech Simics [6]. We use an implementation of the LogTM-SE protocol and the detailed timing model for the memory subsystem of GEMS v2.1, with the Simics in-order processor model.…”

Section: Simulation Methodology and Environmentmentioning

confidence: 99%

Directory-Based Conflict Detection in Hardware Transactional Memory

Titos¹,

Acacio²,

García³

2008

High Performance Computing - HiPC 2008

View full text Add to dashboard Cite

Abstract. One of the key design points of any hardware transactional memory (HTM) system is the conflict detection mechanism, and its efficient implementation becomes critical when conflicts are not a rare event. While many contemporary proposals rely on the coherence protocol to carry out conflict detection at the private cache levels, this approach is not optimal for systems that use a directory to maintain coherence over an unordered, scalable network, such as tiled CMPs. In this paper, we present a new scheme of conflict detection for HTM systems, which moves this key mechanism from the private caches to the directory level. We propose a novel transactional book-keeping method and describe how this detection can be carried out more efficiently at the directory. Simulation results show that our approach obtains reductions in execution time between 25 and 55% for transactional benchmarks with a high number of conflicts, with an average improvement over LogTM-SE of 15%.

show abstract

Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset

Abstract: The Toolset, release 1.0, under GNU GPL [9].

Cited by 1,275 publications

References 19 publications

An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures

An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures

Exploit Temporal Locality of Shared Data in SRC Enabled CMP

Directory-Based Conflict Detection in Hardware Transactional Memory

Contact Info

Product

Resources

About