Multilayer Metallization with Planar Interconnect Structure Utilizing CVD Al2 O 3 Film

Abstract

DIFFUSION OF COBALT 987of the least squares line. This is shown in Fig. 5. The activation energy for diffusion, Q, obtained from the least squares line is Q --28 _ 6 kcal/mole Another point of interest is that the square root relation Vh~ holds for most systems of interest for this model. For gold thicknesses of 3.3 #m and temperature of 50~ (along with the corresponding diffusion coefficient D ----10 -19) the time corresponding to F = 0.6 is of the order of 104 years. If we use smaller thicknesses where the fraction might be appreciable, other transport mechanisms, e.g., porosity, would prevail and the model proposed here would not be applicable. SummaryWe have considered the diffusion of cobalt out of a gold layer. The theory is discussed first to relate measured quantities to diffusion coefficients. Measurements were taken and the appropriate calculations made to obtain values for the diffusion coefficients at different temperatures. Arrhenius plot extrapolations were then made to obtain rough values for the coefficients at lower temperatures. ABSTRACTA new, multilayer metallization system has been developed for the purpose of fabricating a planar interconnect structure. This system comprises two levels of metal interconnection, and the first-level metal layer is buried in a low temperature CVD A12Os film pyrolytically deposited by Al(i-CsH70)3 at 420~ The metal chosen for both layers is aluminum, and the insulator is phosphosilicate glass. In the metal processing, a self-aligned photolithographic technique is applied in which positive photoresist AZ-1350 plays an important role in forming the first-level A1 layer and the A1203 film. * Electrochemical Society Active Member.

Efficient spin injection through a crystalline AlOx tunnel barrier prepared by the oxidation of an ultra-thin Al epitaxial layer on GaAs

“…This method is not used for III-V compound semiconductors because group-V elements, such as As and P, have high vapor pressures. Other methods, the low-temperature plasma anodic oxidation 11 , metal-organic chemical vapor deposition 12 , sputtering 13 , electron beam evaporation 14 , and atomic layer deposition 15 , have been studied with the aim to obtain high quality AlO x layers, but layers obtained from those methods have suffered from a large numbers of interface traps. Density of the interface traps is ∼10 13 cm -2 eV -1 for the AlO x /GaAs systems 16 , which is much higher than that (∼10 9 cm -2 eV -1 ) in the SiO 2 /Si system.…”

Planar Interconnection Technology for LSI Fabrication Utilizing Lift‐off Process

“…In order to solve these problems, planar technology for the interconnection layer has been used. For example, there are several planarization techniques, such as anodic oxidation (1), lift-off (2)(3)(4), glass flow (5), surface leveling (6), polymer film coating (7), and etch back employing RIE (8). Anodic oxidation can form completely planar interconnection metallization (1).…”

“…Thus, it seems that these factors interfere with miniaturizing the LSI's pattern, because it is difficult to further decrease these factors. The lift-off process for surface planarization utilizes A1 evaporation on the photoresist without heating the substrate (2,3). Thus, A1 film has a poor step coverage at the sidewall of the through-hole contact or at the surface step of the underlying film pattern edge.…”