Multiple Addition by Residue Threshold Functions and Their Representation by Array Logic

Parallel counter implementation

“…Table 1 shows that better results can be obtained through the logic optimization described. While the small (7,3) counter is indeed roughly four times the area of the small (3,2) counter, this (7,3) counter is somewhat faster than three times the delay of the (3,2) counter. This effect increases with the larger counter blocks.…”

“…The structure for each of the smaller counters building blocks has been based upon the building block approached described in [6], e.g., the (7,3) counter is construtted with four (3,2) counters. Each of these counter designs has been optimized using the Synopsys Design Compiler.…”

“…An alternate (1023,10) counter design that uses (7,3) and (3,2) counters is shown in figure 6. Only seven stages are required to reduce the initial 1023 row matrix to the equivalent two row matrix.…”

“…Parallel counters are useful in implementing fast multipliers [1], [2], multioperand adders [3], [4], and digital neural networks [5]. Previous counter designs include: quasi-digital [6], threshold gate [1], residue threshold function [3], thermometer code [4], and switching tree logic [7] implementations.…”

“…Design trade-offs are examined regarding the use of counter cells [5], [6], [8], of size ranging from (3,2) to (31,5) as building blocks. The design of the counter blocks will be examined first, followed by four example large counter designs.…”