Parallel counter implementation

Abstract

Abstract. An (n, m) parallel counter is a circuit with n inputs that produces an m-bit binary count of the number of its inputs that are ONEs. This article reports on the design of large parallel counters with up to 1023 inputs. Design trade-offs are examined regarding the use of counter cells of size ranging from (3,2) to (31,5) as building blocks.

Novel architectures for efficient (m, n) parallel counters

“…In successive doubling approach, full adders are used to implement the counters. The synthesized counters are manually optimized [5] or obtained by computer-aided design [6]. These counters have lesser delay but higher hardware complexity than the full adder based counters.…”

“…The switching tree counters shown in [3] are implemented using relay switches but the complexity of this approach grows as the square of the number of inputs. The most popular and widely used existing counters are successive doubling counters [4] and synthesized counters [5,6]. In successive doubling approach, full adders are used to implement the counters.…”

“…A wide variety of parallel counter architectures that exist in literature [4][5][6] have been summarized in [3]. This paper presents new counter architectures that lay emphasis on use of multiplexers to efficiently use outputs of previous stages and improve the overall performance.…”

Saturating counters: application and design alternatives

“…In [1] Jones and Swartzlander have compared the design of parallel counters using only (3,2) or (2,2) counters to designs using more complex counters like (7,3), (15,4) and (31,5). They have analyzed the delay and area of different implementations and concluded that designs based on (3,2) and (2,2) counters only are generally superior.…”

“…Various designs of parallel counters to be used in multiplier units and other applications have been proposed and implemented (e.g., [1,2]). Such designs use different basic building blocks like (3,2) counters, (7,3) counters and the like [3].…”