Novel architectures for efficient (m, n) parallel counters

Veeramachaneni, Sreehari; Lingamneni, Avinash; Krishna, Midhun; Srinivas, M.B.

doi:10.1145/1228784.1228833

Cited by 23 publications

(24 citation statements)

References 7 publications

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“…This conclusion is also emphasized by [14] since the Dada tree is optimum in providing the minimum number of full adders. Dadda showed that the approach can also work for larger adders such as the (7,3) and (15,4). The performance of Wallace and Dadda trees is very similar in terms of delay and power.…”

Section: Related Workmentioning

confidence: 99%

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Low power Wallace multiplier design based on wide counters

Abed

Mohd

Al-bayati

et al. 2011

Circuit Theory & Apps

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Multiplication is one of the most basic arithmetic operations. It is used in digital applications, central processing units, and digital signal processors. In most systems, the multiplier lies within the critical path and hence, due to probability and reliability issues, the power consumption of the multiplier has become very important. Moreover, as chips shrink and their power densities increase, power is becoming a major concern for chip designers. The ever increasing demand for portable applications with their limited battery lifetime indicates that power considerations should be a center stone in today's designs and the future's designs. Thus, all this has motivated us to provide a novel circuit design technique for a low power multiplier without compromising the multiplier's speed.This paper presents a new power aware multiplier design based on Wallace tree structure. A new algorithm is proposed using high-order counters to meet the power constraints imposed by mobility and shrinking technology. Commonly used multipliers of widths 8, 16, and 32 bits are designed based on the proposed algorithm. The new approach has succeeded in reducing the total number of gates used in the multiplier tree. Simulations on Altera's Quartus-II FPGA simulator showed that the design achieves an average of 18.6% power reduction compared to the original Wallace tree. The design performs even better as the multiplier's size increases, achieving a 5% gate count reduction, a 26.5% power reduction, and a 23.9% better power-delay product in 32-bit multipliers.

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Section: Related Workmentioning

confidence: 99%

“…And it cannot produce an all 1s output combination (111) 2 = 7 while a (7,3) counter is saturated. There has been a lot of work on counter design such as in [15,16] to design low power and provide fast counters.…”

Section: Counters and Compressorsmentioning

confidence: 99%

Low power Wallace multiplier design based on wide counters

Abed

Mohd

Al-bayati

et al. 2011

Circuit Theory & Apps

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“…(n+1)) parallel counter that counts the number of logic '1's in an n-bit input and yields Parallel counters are commonly used in fast Optimized CMOS counter have been shown in [15] for and the design complexity has been number of logic gates needed. Designing these gates with WHFM provides a 2X performance gain per unit gate delay.…”

Section: Projected Benefits Over State-of-the-art Scaled Cmos: Inmentioning

confidence: 99%

“…The WHFM implementation requires only 3 logic devices, as opposed to 12 logic gates needed for an optimized CMOS (7, 3) parallel counter [15]. Table II shows how logic complexity scales for WHFM and CMOS versions of the parallel counter.…”

Section: Projected Benefits Over State-of-the-art Scaled Cmos: Inmentioning

confidence: 99%

“…As input width scales, significant reductions in design complexity are obtained. (e.g., 8X fewer logic gates for (15,4) and 15X fewer logic gates for (31, 5) counter). Performance improvements in conjunction with reductions in the logic complexity could enable new types of algorithms and efficient computational models in the future.…”

Section: Projected Benefits Over State-of-the-art Scaled Cmos: Inmentioning

confidence: 99%

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Towards logic functions as the device

Shabadi

Khitun

Narayanan

et al. 2010

2010 IEEE/ACM International Symposium on Nanoscale Architectures

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-This paper argues for alternate state variables and new types of sophisticated devices that implement more functionality in one computational step than typical devices based on simple switches. Elementary excitations in solids enabling wave interactions are possible initial candidates to create such new devices. The paper focuses on magnon-based spin-wave-logic functions (SPWF) and presents high fan-in majority, weighted high fan-in majority, and frequency-multiplexed weighted high fan-in majority devices as initial SPWFs. Experiments proving feasibility are also shown. Benefits vs. scaled CMOS are quantified. Results show that for 128 or larger inputs even a 2.5µm SPWF carry-look-ahead adder implementation is faster than the 45nm CMOS version. The 45nm SPWF adder is expected to be significantly faster across the whole range of input widths. In particular, the 45nm SPWF CLA adder is estimated to be at least 77X faster than CMOS version for input widths equal to or greater than 1024. A second example of a counter circuit is presented to illustrate the considerable reduction in complexity possible vs. CMOS.

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de Dinechin,

Kumm

2023

Application-Specific Arithmetic

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Novel architectures for efficient (m, n) parallel counters

Cited by 23 publications

References 7 publications

Low power Wallace multiplier design based on wide counters

Low power Wallace multiplier design based on wide counters

Towards logic functions as the device

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