Multiple test set generation method for LFSR-based BIST

Shi, Youhua; Zhang, Zhe

doi:10.1145/1119772.1119962

Cited by 6 publications

(9 citation statements)

References 9 publications

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“…To overcome the inefficiency problem of pseudo random patterns in detecting random-pattern-resistant (r.p.r) faults, various BIST methods that are capable of applying additional deterministic patterns [2][3][4][5][6][7][8][9][10][11][12][13][14][15] or generate only deterministic patterns [16][17][18] are proposed. These deterministic patterns can be generated via reseeding [2-5, 10-13, 16-18] or through some additional specific logic such as mapping logic [14][15]. Each seed is then used to derive a sequence of test patterns via LSFR or twisted-ring-counter (TRC) [16][17][18] operations to cover other faults.…”

Section: Introductionmentioning

confidence: 99%

“…These BIST methods can generally be classified into test-per-scan [2][3][4][5][6][7][8][9][10] and test-per-clock [11][12][13][14][15][16][17][18] methods according to their test application schemes. The test-per-scan method serially loads one test pattern into scan chains bit-by-bit.…”

Section: Introductionmentioning

confidence: 99%

“…Compared with previous test-per-clock methods [11][12][13][14][15][16][17][18], our reseeding technique has the following distinguishing features. 1) Instead of selecting a seed from a predefined test set, our algorithm will determine each seed by starting with a fully unspecified pattern.…”

Section: Introductionmentioning

confidence: 99%

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A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data Volume

Lien

Lee

Hsieh

2012

2012 IEEE 21st Asian Test Symposium

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This paper proposes a new test-per-clock BIST method that attempts to minimize the test sequence length and the test data volume simultaneously. An efficient LFSR reseeding algorithm is developed by which each determined seed together with its derived patterns can detect the maximum number of so far undetected faults. During the seed determination process an adaptive X-filling process is first employed to generate a set of candidate patterns for pattern embedding. The process then derives a seed solution that can embed multiple candidate patterns at one time so as to minimize the number of seeds. To shorten the test sequence, the pattern embedding process begins with a small initial set of pseudo-random patterns and will incrementally add more patterns only when necessary. Experimental results show that compared with the previous test-per-clock techniques based on the LFSR-and twisted-ring-counter-reseeding methods, our method can reduce the test sequence length by over 60% with generally smaller numbers of storage bits. When compared with the mapping-logic-based BIST methods, our method can reduce the test sequence length by over 50% with a comparable area overhead.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data Volume

Lien

Lee

Hsieh

2012

2012 IEEE 21st Asian Test Symposium

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“…A proposed method for this is a reseeding technique, where the seed in the LFSR is reprogrammed automatically in order to test for certain vectors that may occur in the normal operating mode [11].…”

Section: Built In Self Testmentioning

confidence: 99%

“…LFSRs have many common uses including pseudorandom number generators and cryptography [10]. Another common use of LFSRs is built in self testing (BIST), which generates test vectors to the system and an output ROM to compare the results to expected values [11].…”

Section: Introductionmentioning

confidence: 99%

A high performance, hybrid wave-pipelined linear feedback shift register with skew tolerant clocks

Nyathi

Delgado-Frias

2003 46th Midwest Symposium on Circuits and Systems

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Chair: Jabulani Nyathi Clock skew and clock distribution are increasingly becoming a major design concern in high performance, high density synchronous systems. Large clock networks are required for efficient clock distribution and they contribute significantly to the power dissipated by the system, while clock skew takes up a considerable percentage of the clock period.Design effort for clock networks is currently estimated to take up 20% of system design time, while power dissipation due to the clock network is reported to be 30% of the total dissipation. It is therefore necessary to investigate the possibilities of other schemes that could results in cost reduction by avoiding complicated architectures while facilitating fast logic.We explore the possibility of managing clock skew and reducing clock loading by applying the hybrid wave-pipelining scheme to a linear feedback shift register. The hybrid wave-pipelining scheme takes advantage of interconnects and data path delays to optimize clock skew and allows the clock to "travel" with its associated data. The system's clock in conjunction with stage delays is used to generate wave-pipelined clocks that have short cycle times and are skew tolerant. The hybrid wave-pipelined clock is designed to mimic the data path elements of the LFSR stage, thus reducing the uncontrolled clock skew, as well as clock loading. Thus, the iv resulting skew is a result of the data path circuitry. A LFSR would provide a good means of measuring clock skew since the common edge of the clock triggers data transfer.Linear feedback shift registers also have numerous common uses including pseudorandom number generator, random pattern generator and analyzer, encryption/decryption and direct sequence spread spectrum for digital signal processing. Their study with different clocking schemes is beneficial as LFSRs are easy to analyze and are found in many applications as mentioned.In this thesis, it is shown that the use of hybrid wave-pipelining provides significant clock skew improvements (six times) compared with a buffered clock design, and also offers improved clock cycle time. There is also potential for a reduction in power dissipation associated with the clock trees, since the scheme reduces the need for complicated clock distribution networks.

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A Novel TPG Method for Reducing BIST Test-Vector Size

Zhang

2007

High Density Design Packaging and Microsystem Integration, 2007 International Symposium On

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Multiple test set generation method for LFSR-based BIST

Cited by 6 publications

References 9 publications

A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data Volume

A Test-Per-Clock LFSR Reseeding Algorithm for Concurrent Reduction on Test Sequence Length and Test Data Volume

A high performance, hybrid wave-pipelined linear feedback shift register with skew tolerant clocks

A Novel TPG Method for Reducing BIST Test-Vector Size

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