Multiplexed trace signal selection using non-trivial implication-based correlation

Prabhakar, Sandesh; Hsiao, Michael S.

doi:10.1109/isqed.2010.5450503

Cited by 14 publications

(5 citation statements)

References 15 publications

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“…These are achieved in this fact to maximize internal visibility. The selection techniques like Chatterjee et al [Chatterjee, McCarter and Bertacco (2011); Prabhakar and Hsiao (2010); Han, Yang and Abraham (2013)] have been proposed which is focused only on state restoration, not on error detection. The timing errors have been detected recently and these approaches are based on the same set of signals (i.e., static signals) for complete execution of the system.…”

Section: Background and Related Workmentioning

confidence: 99%

Region-Aware Trace Signal Selection Using Machine Learning Technique for Silicon Validation and Debug

Agalya¹,

Muthaiah²,

Muralidharan³

2019

Computer Modeling in Engineering &Amp; Sciences

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In today's modern design technology, post-silicon validation is an expensive and composite task. The major challenge involved in this method is that it has limited observability and controllability of internal signals. There will be an issue during execution how to address the useful set of signals and store it in the on-chip trace buffer. The existing approaches are restricted to particular debug setup where all the components have equivalent prominence at all the time. Practically, the verification engineers will emphasis only on useful functional regions or components. Due to some constraints like clock gating, some of the regions can be ignored during execution. Likewise, some of these regions can be verified deeply and have minimum errors compared to other control regions. The proposed system focusses on random signals that identify more errors which are prone to signal selection technique with low area overhead. To enhance the observability, a machine learning technique is developed. Based on the training samples of smaller designs, a model is developed to find out the contiguous neighbours of each flip-flop. This can eliminate the obstacles of unknown signals. This system demonstrates using Opencores and ISCAS'89 benchmark circuits that result in easy and fast error detection compared to the state-of-theart of other methods. This is also verified using gate-level error models by cross-validation of each debug run.

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Section: Background and Related Workmentioning

confidence: 99%

Region-Aware Trace Signal Selection Using Machine Learning Technique for Silicon Validation and Debug

Agalya¹,

Muthaiah²,

Muralidharan³

2019

Computer Modeling in Engineering &Amp; Sciences

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“…All of these approaches perform static signal selection i.e., the same set of signals are traced during the entire execution. The procedure developed by Prabhakar et al [10] alternates between two sets of signals in alternate cycles. As a result, it is a very specific case of temporal distribution of errors without any consideration for spatial distribution.…”

Section: Related Workmentioning

confidence: 99%

Dynamic Selection of Trace Signals for Post-Silicon Debug

Basu

Mishra

Patra

et al. 2013

2013 14th International Workshop on Microprocessor Test and Verification

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Post-silicon validation is one of the most expensive and complex tasks in today's System-on-Chip (SoC) design methodology. A major challenge in post-silicon debug is limited observability of the internal signals. Existing approaches address this issue by selecting a small set of useful signals. These signal states are stored in an on-chip trace buffer during execution. The applicability of existing methods is limited to a specific debug scenario where every component has equal importance all the time. In reality, a verification engineer would like to focus on a specific set of components (functional regions). Some regions can be ignored in a certain duration during execution due to clock gating and other considerations. Similarly, certain regions may be well verified datapath and less likely to have errors compared to other controlintensive regions. In this paper, we propose an efficient signal selection algorithm and a low-overhead trace controller design that would enable verification engineers to dynamically select a set of trace signals for improved error detection. Our experimental results using both ISCAS'89 benchmarks and Opencores circuits demonstrate that our approach can detect up to 3 times more errors compared to existing techniques.

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“…Many solutions have been proposed in the literature to tackle this problem [17][18][19][20][21][22][23][24]. On the other hand, due to the limited trace bandwidth, we are not able to trace all the tapped signals concurrently in each debug run.…”

Section: Preliminaries and Motivationmentioning

confidence: 99%

On efficient silicon debug with flexible trace interconnection fabric

Liu

2012

2012 IEEE International Test Conference

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Trace-based debug solutions facilitate to eliminate bugs escaped from pre-silicon verification and have gained wide acceptance in the industry. Generally speaking, a number of "key" signals in the circuit are tapped, but not all of them can be observed at the same time due to the limited trace bandwidth. Therefore, a trace interconnection fabric is utilized to output either a subset of signals with multiplexor (MUX) network or compressed signatures with XOR network to the trace memory/port in each debug run. However, both kinds of trace interconnection fabrics have limitations. On one hand, with MUX-based fabric, the visibility of the circuit is limited and it requires many debug runs to locate errors. On the other hand, with XOR-based fabric, typically clean "golden vectors" (i.e, without unknown bits) are required so that signatures are not corrupted. In this paper, we propose a flexible trace interconnection fabric design that is able to overcome the above limitations, at the cost of little extra design-for-debug hardware. Experimental results on benchmark circuits demonstrate the effectiveness of the proposed technique.

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Multiplexed trace signal selection using non-trivial implication-based correlation

Cited by 14 publications

References 15 publications

Region-Aware Trace Signal Selection Using Machine Learning Technique for Silicon Validation and Debug

Region-Aware Trace Signal Selection Using Machine Learning Technique for Silicon Validation and Debug

Dynamic Selection of Trace Signals for Post-Silicon Debug

On efficient silicon debug with flexible trace interconnection fabric

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