2009 15th International Conference on Parallel and Distributed Systems 2009
DOI: 10.1109/icpads.2009.118
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Multiprocessor System-on-Chip Profiling Architecture: Design and Implementation

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Cited by 7 publications
(5 citation statements)
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“…On the other hand, FPGA systems require a hardware-aware profiler. Some contributions have been achieved in work [39][40][41]. The University of Toronto has implemented a snooping software profiler to count the total number of cycles during an application execution [39].…”
Section: Exploitation Of the Proposed Methodologymentioning
confidence: 99%
See 1 more Smart Citation
“…On the other hand, FPGA systems require a hardware-aware profiler. Some contributions have been achieved in work [39][40][41]. The University of Toronto has implemented a snooping software profiler to count the total number of cycles during an application execution [39].…”
Section: Exploitation Of the Proposed Methodologymentioning
confidence: 99%
“…It inserts software drivers around the software function blocks to enable or disable particular counters implemented in Airwolf. For the multiprocessor systems, a multiprocessor profiling architecture is introduced for MPSoC embedded systems [41]. These FPGA-based tools have the similar functionalities as PMCs on the embedded processors or general purpose processor.…”
Section: Exploitation Of the Proposed Methodologymentioning
confidence: 99%
“…Hardware performance counters consist of two components-event detectors and event counters [18]. Users can configure performance event detectors to detect performance events as cache misses, cycles consumed, or branch mispredictions.…”
Section: Hpc Profilesmentioning
confidence: 99%
“…Certain profilers are customized to profile single task (thread) applications whereas certain profilers are able to profile multi task (thread) applications [7]. Profilers customized for multitask applications, can also profile Operating System based applications.…”
Section: Classification Based On Task Supportedmentioning
confidence: 99%