Multiscale 3D thermal analysis of analog ICs: From full-chip to device level

Turowski, Marek; Dooley, Sarah; Raman, Ashok; Casto, Matthew

doi:10.1109/therminic.2008.4669880

Cited by 3 publications

(2 citation statements)

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“…The active region of the top die is connected to the bottom die by means of Cu through-Si vias (TSVs) through the top die [12]. These vias have a diameter of 5 mm. Several pitches of the TSVs are considered to study the effect of the TSV on the thermal behavior or the stack.…”

Section: Methodsmentioning

confidence: 99%

“…Furthermore the thermal analysis should be included in the design loop to assess the thermal consequences of design iterations and verify the final design before sign-off. Turowski et al [5] presented a multiscale analysis for a single die. [3,[6][7][8]] present a compact model approach using transfer functions for a thermal analysis on a higher level of abstraction for a stacked die structure.…”

Section: Introductionmentioning

confidence: 99%

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Fine grain thermal modeling and experimental validation of 3D-ICs

Oprins

Srinivasan

Cupak

et al. 2011

Microelectronics Journal

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3D die stacking is a promising technique to allow miniaturization and performance enhancement of electronic systems. Key technologies for realizing 3D interconnect schemes are the realization of vertical connections, either through the Si die or through the multilayer interconnections. The complexity of these structures combined with reduced thermal spreading in the thinned dies complicate the thermal analysis of a stacked die structure. In this paper a methodology is presented to perform a detailed thermal analysis of stacked die packages including the complete back end of line structure (BEOL), interconnection between the dies and the complete electrical design layout of all the stacked dies. The calculations are performed by 3D numerical techniques and the approach allows importing the full electrical design of all the dies in the stack. The methodology is demonstrated on a 2 stacked die structure in a BGA package. For this case the influence of through-Si vias (TSVs) on the temperature distribution is studied. The modeling results are experimentally validated with a dedicated test vehicle. A thermal test chip with integrated heaters and diodes as thermals sensors is used to successfully validate the detailed temperature profile of the hot spots in the top die of the die stack.

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Section: Methodsmentioning

confidence: 99%