Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications

Barretta, Domenico; Fornaciari, William; Sami, Mariagiovanna; Bagni, Daniele

doi:10.1109/date.2005.219

Cited by 5 publications

(6 citation statements)

References 5 publications

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“…In [2], a quite different approach for clustered VLIWs is taken. The processor has two modes: single threaded and multithreaded.…”

Section: Introductionmentioning

confidence: 99%

“…With such approach, a significant amount of horizontal waste is removed. In addition, 1 Cycles where no operations are issued 2 Operation slot inside a VLIW with a nop by marking threads that produce events like cache misses as blocked, vertical waste is also removed. Finally, CSMT does not degrade single thread performance since all resources are available when a single thread is present.…”

Section: Introductionmentioning

confidence: 99%

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Cluster-level simultaneous multithreading for VLIW processors

Gupta

Sánchez

Llosa

2007

2007 25th International Conference on Computer Design

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Clustered VLIW embedded processors have become widespread due to benefits of simple hardware and low power. However, while some applications exhibit large amounts of instruction level parallelism (ILP) and benefit from very wide machines, others have little ILP, which wastes precious resources in wide processors. Simultaneous MultiThreading (SMT) is a well known technique that improves resource utilization by exploiting thread level parallelism at the instruction grain level. However, implementing SMT for VLIWs requires complex structures. In this paper, we propose CSMT (Cluster-level Simultaneous MultiThreading) to allow some degree of SMT in clustered VLIW processors with minimal hardware cost and complexity. CSMT considers the set of operations that execute simultaneously in a given cluster (named bundle) as the assignment unit. All bundles belonging to a VLIW instruction from a given thread are issued simultaneously. To minimize cluster conflicts between threads, a very simple hardwarebased cluster renaming mechanism is proposed. The experimental results show that CSMT significantly improves ILP when compared with other multithreading approaches suited for VLIW. For instance, with 4 threads CSMT shows an average speedup of 113% over a single-thread VLIW architecture and 36% over Interleaved MultiThreading (IMT). In some cases, speedup can be as high as 228% over single thread architecture and 97% over IMT.

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“…In [2], a quite different approach for clustered VLIWs is taken. The processor has two modes: single threaded and multithreaded.…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Cluster-level simultaneous multithreading for VLIW processors

Gupta

Sánchez

Llosa

2007

2007 25th International Conference on Computer Design

View full text Add to dashboard Cite

show abstract

“…In the latter case, threads have been compiled to use only a single cluster. A similar approach, Multithreaded extension to clustered VLIWs [3] also uses compiler generated threads to run multiple threads on a clustered VLIW processor.…”

Section: Other Related Workmentioning

confidence: 99%

Hybrid multithreading for VLIW processors

Gupta

Sánchez

Llosa

2009

Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

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Several multithreading techniques have been proposed to reduce resource underutilization in Very Long Instruction Word (VLIW) processors. Simultaneous MultiThreading (SMT) is a popular technique that improves processor performance by issuing multiple instructions from different threads. In VLIW processors, SMT requires extra hardware to merge instructions from different threads. The complexity of this hardware increases substantially with the number of threads. On the other hand, techniques like Interleaved MultiThreading (IMT) do not need any merging hardware, and support a larger number of threads at reasonable cost. In this paper, we propose Hybrid MultiThreading (HMT), a technique that at each cycle merges instructions from only a subset of threads. HMT supports a reasonable number of threads with a low merging hardware cost. For instance, it is possible to support 8 hardware threads with a merging hardware for only 2 threads. The experimental results show that using HMT improves the multithreading performance significantly. Further, supporting 8 hardware threads with HMT but using a 4-thread merging hardware achieves a performance similar to merging 8 threads simultaneously with a significantly lower merging hardware cost.

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“…The multithreaded version of the reference processor is described in [18] and allows each cluster to execute a different thread. Since this approach is very scalable, we will consider for simplicity a processor that is composed of two clusters.…”

Section: The Reference Architecturementioning

confidence: 99%

Energy/Performance Evaluation of the Multithreaded Extension of a Multicluster VLIW Processor

Barretta

Palermo

Sami

et al.

Seventh International Workshop on Computer Architecture for Machine Perception (CAMP'05)

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Abstract-In this paper we address the problem of the architectural exploration from the energy/performance point of view of a VLIW processor for embedded systems. We also consider an architectural modification we introduced in order to extend the reference processor so that it can exploit both instruction level parallelism and thread level parallelism. A power model obtained by applying an instruction-level power estimation technique is presented and validated with experimental results. This power model was plugged in a parametric cycle-accurate simulator in order to support architectural exploration. Experimental results derived from the proposed framework show a comparison among different implementations of the reference processor: single and dual cluster implementations, and dual cluster with multithreaded extension.

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Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications

Abstract: Abstract

Cited by 5 publications

References 5 publications

Cluster-level simultaneous multithreading for VLIW processors

Cluster-level simultaneous multithreading for VLIW processors

Hybrid multithreading for VLIW processors

Energy/Performance Evaluation of the Multithreaded Extension of a Multicluster VLIW Processor

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