Multithreaded Processors

Abstract

The instruction-level parallelism found in a conventional instruction stream is limited. Studies have shown the limits of processor utilization even for today's superscalar microprocessors. One solution is the additional utilization of more coarse-grained parallelism. The main approaches are the (single) chip multiprocessor and the multithreaded processor which optimize the throughput of multiprogramming workloads rather than single-thread performance. The chip multiprocessor integrates two or more complete processors on a single chip. Every unit of a processor is duplicated and used independently of its copies on the chip. In contrast, the multithreaded processor is able to pursue two or more threads of control in parallel within the processor pipeline. Unused instruction slots, which arise from pipelined execution of single-threaded programs by a contemporary microprocessor, are filled by instructions of other threads within a multithreaded processor. The execution units are multiplexed between the threads in the register sets. Underutilization of a superscalar processor due to missing instruction-level parallelism can be overcome by simultaneous multithreading, where a processor can issue multiple instructions from multiple threads each cycle. Simultaneous multithreaded processors combine the multithreading technique with a wideissue superscalar processor such that the full issue bandwidth is utilized by potentially issuing instructions from different threads simultaneously. This survey paper explains and classifies the various multithreading techniques in research and in commercial microprocessors and compares multithreaded processors with chip multiprocessors.

Timed Petri Nets in Performance Exploration of Simultaneous Multithreading

“…Instruction-level multithreading [9], [10], [1] is a technique of tolerating long-latency memory accesses by switching to another thread (if it is available for execution) rather than waiting for the completion of the long-latency operation. If different threads are associated with different sets of processor registers, switching from one thread to another (called "context switching") can be done very efficiently [11], in one or just a few processor cycles.…”

Dynamic Instruction Scheduling in a Trace-based Multi-threaded Architecture

“…This is a problem with all ILP architectures, both statically (compiled-based) and dynamically scheduled, but it is exacerbated by the multi-threading. All these are well-known advantages and disadvantages of multi-threading, as has been well documented elsewhere [2,6,7]. A second area of concern is the increase in the number of VLIW blocks that need to be stored and thus a pressure for an increase in the capacity of this cache.…”

“…The last seriously impacts on performance through vertical wastage (processor cycles where no instructions can be issued) from the long fetch-issue pipeline. Thus, the simultaneous multithreading of superscalars is no longer seriously considered because of their complexity [1], although they are of interest as single-threaded processors within Chip Multiprocessors [2] (CMPs). In pure VLIW systems, the compiler has complete responsibility for creating a package of operations that can be simultaneously issued to the VLIWs many PEs.…”

Foxels for high flux, high resolution computed tomography (foxelct) Using broad x-ray focal spots

“…The computers will catch up. For example, each slice could be run in a different thread in a multicore computer [284,285], and CT algorithms that take advantage of parallel computers [2,[286][287][288][289][290] are available.…”