MultPIM: Fast Stateful Multiplication for Processing-in-Memory

Leitersdorf, Orian; Ronen, Ronny; Kvatinsky, Shahar

doi:10.1109/tcsii.2021.3118215

Cited by 18 publications

(2 citation statements)

References 27 publications

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“…The main optimization of the memristive multiplier (mMP) comes from reducing the partial products, which have been attempted by shift-and-add, Wallace-tree, and Dadda. [50][51][52][53][54] When utilizing the massive parallelism of the CBA structure and IMC, the operation speed of the mMP can be enhanced, while the area overhead remains minimal. In this work, a new mMP design is proposed using improved Ex-logic FAS with the modified Wallace-tree algorithm.…”

Section: Memristive Multipliers Using Ex-logic Gatesmentioning

confidence: 99%

Reliable Domain‐Specific Exclusive Logic Gates Using Reconfigurable Sequential Logic Based on Antiparallel Bipolar Memristors

Park

Kim

et al. 2022

Advanced Intelligent Systems

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The development of memristor‐based stateful logic circuits can minimize data movement during the computing process to achieve in‐memory computing, mitigating the von Neumann bottleneck in the current computing architecture. Herein, a method to combine resistance–resistance (R–R) and voltage–resistance (V–R) logic gates to implement exclusive logic gates composed of APMR‐two‐2(XOR, IMP, RIMP) and APMR‐three‐4XOR, where APMR means antiparallel memristors with a series resistor, is suggested. The proposed gates can accelerate XOR logic operation in a single cycle and expand for the n‐bit input. The performance of the proposed logic gate is then demonstrated with a 1‐bit full adder–subtractor along with the comparison of an n‐bit ripple carry adder. It shows that the implementation for the n‐bit adder takes 4n+1 memristors within 2n+1 steps, which significantly improves the optimization in terms of space‐ and time‐related costs compared with other memristive logic gates. Subsequently, the improved adder circuit can be further utilized to implement an n‐bit multiplier. In addition, the evaluation of the device stress on the various logic gates confirms that the proposed logic gates are reliable.

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Section: Memristive Multipliers Using Ex-logic Gatesmentioning

confidence: 99%

Reliable Domain‐Specific Exclusive Logic Gates Using Reconfigurable Sequential Logic Based on Antiparallel Bipolar Memristors

Park

Kim

et al. 2022

Advanced Intelligent Systems

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“…In stateful logic gates, the input and output are represented in the form of resistance, and the result is written during the computation directly to the output memory cell without reading the input cells beforehand or moving any data outside the memory array [10]. When the stateful logic gates are functionally complete (e.g., NOR gates), any desired function can be computed using a sequence of stateful logic operations [11]- [13]. Stateful logic enables PIM architectures such as the memristive memory processing unit (mMPU) [14] and RACER [15] that offer massive intrinsic parallelism, highperformance, and energy-efficient processing, while maintaining backward compatibility with von Neumann architectures.…”

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confidence: 99%

Stateful Logic Using Phase Change Memory

Hoffer

Wainstein

Neumann

et al. 2022

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Stateful logic is a digital processing-in-memory technique that could address von Neumann memory bottleneck challenges while maintaining backward compatibility with standard von Neumann architectures. In stateful logic, memory cells are used to perform the logic operations without reading or moving any data outside the memory array. Stateful logic has been previously demonstrated using several resistive memory types, mostly by resistive RAM (RRAM). Here we present a new method to design stateful logic using a different resistive memoryphase change memory (PCM). We propose and experimentally demonstrate four logic gate types (NOR, IMPLY, OR, NIMP) using commonly used PCM materials. Our stateful logic circuits are different than previously proposed circuits due to the different switching mechanism and functionality of PCM compared to RRAM. Since the proposed stateful logic form a functionally complete set, these gates enable sequential execution of any logic function within the memory, paving the way to PCM-based digital processing-in-memory systems.Index Terms-phase-change-memory (PCM), processing-inmemory (PIM), stateful-logic I. INTRODUCTIONF OR the last 75 years, computers have been typically designed in the von Neumann architecture, which separates the memory from the processing units. While their programming model is simple, incessant data movement limits system performance because memory access time is often substantially longer than the computing time. This bottleneck has worsened over the years since CPU speed has improved more than memory speed and bandwidth (the so-called 'memory wall') [1]. One attractive approach to deal with this problem is processing-in-memory (PIM), which suggests adding computation capabilities to the memory. PIM reduces the need for costly (in terms of processing-speed, bandwidth, and energy) chip-to-chip transfers, thus yielding higher performance and energy efficiency [2].An increasing number of applications from highperformance computing (HPC) to databases, data analytics and deep neural networks require higher memory capacity to meet the needs of workloads with large data sets. DRAM scaling has slowed down in the last years, and it has become Manuscript

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Achieving the Performance of All-Bank In-DRAM PIM With Standard Memory Interface: Memory-Computation Decoupling

et al. 2022

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Processing-in-Memory (PIM) has been actively studied to overcome the memory bottleneck by placing computing units near or in memory, especially for efficiently processing low locality dataintensive applications. We can categorize the in-DRAM PIMs depending on how many banks perform the PIM computation by one DRAM command: per-bank and all-bank. The per-bank PIM operates only one bank, delivering low performance but preserving the standard DRAM interface and servicing non-PIM requests during PIM execution. The all-bank PIM operates all banks, achieving high performance but accompanying design issues like thermal and power consumption. We introduce the memory-computation decoupling execution to achieve the ideal all-bank PIM performance while preserving the standard JEDEC DRAM interface, i.e., performing the per-bank execution, thus easily adapted to commercial platforms. We divide the PIM execution into two phases: memory and computation phases. At the memory phase, we read the bank-private operands from a bank and store them in PIM engines' registers bank-by-bank. At the computation phase, we decouple the PIM engine from the memory array and broadcast a bank-shared operand using a standard read/write command to make all banks perform the computation simultaneously, thus reaching the computing throughput of the all-bank PIM. For extending the computation phase, i.e., maximizing all-bank execution opportunity, we introduce a compiler analysis and code generation technique to identify the bank-private and the bank-shared operands. We compared the performance of Level-2/3 BLAS, multi-batch LSTM-based Seq2Seq model, and BERT on our decoupled PIM with commercial computing platforms. In Level-3 BLAS, we achieved speedups of 75.8x, 1.2x, and 4.7x compared to CPU, GPU, and the per-bank PIM and up to 91.4% of the ideal all-bank PIM performance. Furthermore, our decoupled PIM consumed less energy than GPU and the per-bank PIM by 72.0% and 78.4%, but 7.4%, a little more than the ideal all-bank PIM.INDEX TERMS Memory-computation decoupling, in-memory processing, standard memory interface, all-bank execution.

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MultPIM: Fast Stateful Multiplication for Processing-in-Memory

Cited by 18 publications

References 27 publications

Reliable Domain‐Specific Exclusive Logic Gates Using Reconfigurable Sequential Logic Based on Antiparallel Bipolar Memristors

Reliable Domain‐Specific Exclusive Logic Gates Using Reconfigurable Sequential Logic Based on Antiparallel Bipolar Memristors

Stateful Logic Using Phase Change Memory

Achieving the Performance of All-Bank In-DRAM PIM With Standard Memory Interface: Memory-Computation Decoupling

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