MUTE-AES: A multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm

Ambrose,; Parameswaran, Sri; Ignjatovic,

doi:10.1109/iccad.2008.4681650

Cited by 34 publications

(18 citation statements)

References 14 publications

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“…Applying these techniques to multiproces sor systems are not straightforward and will increase area and power as suggested in [9]. This is not viable for an embedded system where area and power are one of the important con straints.…”

Section: Rel Ated Workmentioning

confidence: 97%

“…On the other hand the multiprocessor balancing architecture (MUTE), proposed in [9], incurs much lower DPA values and no significant spikes, hence thwarting the adversary's attempt in realizing the secret key. When a normal processor is executing a cryptographic application, MUTE attaches another balancing processor in the MPSoC (there can be more processors) which executes the comple mentary version of the same application.…”

Section: Motivationmentioning

confidence: 99%

“…Hence a careful design and imple mentation is necessary for cryptographic programs and other safety critical applications to make sure there is no useful information in side channels. As far as we are aware, the only multiprocessor solution exists to prevent power analysis side channel attacks is [9]. The technique in [9] utilizes a second (balancing) processor as shown in Figure I, when an encryp tion is executed on a processor, executing the complementary version of the original application in parallel, masking the actual computation.…”

Section: Introductionmentioning

confidence: 99%

“…As far as we are aware, the only multiprocessor solution exists to prevent power analysis side channel attacks is [9]. The technique in [9] utilizes a second (balancing) processor as shown in Figure I, when an encryp tion is executed on a processor, executing the complementary version of the original application in parallel, masking the actual computation. Inspired by this approach, we propose an extension to this solution, to handle its weaknesses and produce a better and en hanced secure design.…”

Section: Introductionmentioning

confidence: 99%

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CoRaS: A multiprocessor key corruption and random round swapping for power analysis side channel attacks: A DES case study

Ambrose

Ignjatović

Parameswaran

2012

2012 IEEE International Symposium on Circuits and Systems

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Ahstract-Multiprocessor System-on-Chip (MPSoC) is an in tegral element in state-of-the-art embedded devices, ranging from low-end, mobile phones, PDAs, handheld medical devices up to high-end cars, avionics and robotics. Proper and safe functionality of such embedded systems is mandatory to avoid severe consequences, whereas security is absolutely necessary with "Cashless Wallets" forecasted to be the only means of financial transactions in the near future. Such a scenario places immense onus on the security experts where secure transactions using credit cards or mobile phones or any other embedded devices should not be revealing any footprint to the adversary. Side Channel Attacks (SCA) are considered as one of the most effective attacks on these embedded systems because of their effectiveness in realizing the secret information without physically disassembling the device. We propose an MPSoC architecture to prevent power analysis SCA where a dual-core algorithmic balancing is enforced by corrupting the balanced key and swapping the encryption rounds of a block-cipher at random places, random number of times. A case study using DES cryptography is performed. Our approach, CoRaS, alleviates performance by 0.1 % and area by 3.6% compared to the state-of-the-art MPSoC solution, however enhances security and practicality by eliminating its weaknesses.

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Section: Rel Ated Workmentioning

confidence: 97%

Section: Motivationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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CoRaS: A multiprocessor key corruption and random round swapping for power analysis side channel attacks: A DES case study

Ambrose

Ignjatović

Parameswaran

2012

2012 IEEE International Symposium on Circuits and Systems

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“…For example, at a low-level the concept of specialist logic styles [22,23] can be considered; at a higher level options such as MUTE-AES [2] are possible. In the latter, the idea is to have two processors execute the same operation in lock-step, but ensure one computes with intermediate data that is the complement of the other: in essence, power consumption is balanced at each step of computation.…”

Section: Countermeasuresmentioning

confidence: 99%

On reconfigurable fabrics and generic side-channel countermeasures

Beat

Grabher

Page

et al. 2012

22nd International Conference on Field Programmable Logic and Applications (FPL)

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Abstract. The use of field programmable devices in security-critical applications is growing in popularity; in part, this can be attributed to their potential for balancing metrics such as efficiency and algorithm agility. However, in common with non-programmable alternatives, physical attack techniques such as fault and power analysis are a threat. We investigate a family of next-generation field programmable devices, specifically those based on the concept of time sharing, within this context: our results support the premise that extra, inherent flexibility in such devices can offer a range of possibilities for low-overhead, generic countermeasures against physical attack.

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