MVL circuit design and characterization at the transistor level using SUS-LOC

Kinvi-Boh, E.; Aline, Michel; Sentieys, Olivier; Olson, E.

doi:10.1109/ismvl.2003.1201392

Cited by 14 publications

(7 citation statements)

References 12 publications

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“…three-valued logic system). It has also been shown that numerous mathematical functions can be operated with fewer operations in ternary logic leading to an overall advantage over binary logic in terms of area, delay and power [7]. However, the added complexity during fabrication and the overall unfamiliarity with multi-valued algebra has kept ternary computation a relatively smaller field.…”

mentioning

confidence: 99%

Design of a ternary static memory cell using carbon nanotube-based transistors

You

Nepal

2011

Micro Nano Lett.

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In this Letter, the authors investigate the use of carbon nanotube-based field effect transistors (CNTFET) for the design of a ternary static random access memory (SRAM). The authors consider two designs-one using 8 transistors and the other using 14 transistors. Using circuit simulation models for CNTFETs, the authors show that both designs produce a functional ternary SRAM cell. The authors also measure the delay and power of the read-and-write operation of the ternary SRAM created using both models and show that the delays are comparable.

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mentioning

confidence: 99%

Design of a ternary static memory cell using carbon nanotube-based transistors

You

Nepal

2011

Micro Nano Lett.

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“…SUSLOC MVL circuits theoretically offer a stable circuit implementation structure for any integer radix, and also allow the use of readily available circuit elements to construct logic circuits. Previous work has utilized SUSLOC technology for ternary systems [23][24][25][26][27]. Insulated gate Field Effect Transistors (FET) are used as the basic building blocks for SUSLOC circuits.…”

Section: A Susloc Circuit Structurementioning

confidence: 99%

Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits

Datla

Thornton

2010

2010 40th IEEE International Symposium on Multiple-Valued Logic

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“…Several Researchers have developed multi-valued non-volatile circuits and memory using non-ferroelectric standard transistors [3]. These circuits allow multilevel storage of data.…”

Section: Multi-level Volatile Cmosmentioning

confidence: 99%

Design of a Multi-Level/Analog Ferroelectric Memory Device

MacLeod

Phillips

2007

Integrated Ferroelectrics

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Increasing the memory density and utilizing the novel characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used a reference to determine the amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. It is predicted that each memory cell may be able to store 8 bits or more. The design is based on data taken from actual ferroelectric transistors. Although the circuit has not been fabricated, a prototype circuit is now under construction. The design of this circuit is different than multi-level FLASH or silicon transistor circuits. The differences between these types of circuits are described in this paper. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.

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MVL circuit design and characterization at the transistor level using SUS-LOC

Cited by 14 publications

References 12 publications

Design of a ternary static memory cell using carbon nanotube-based transistors

Design of a ternary static memory cell using carbon nanotube-based transistors

Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits

Design of a Multi-Level/Analog Ferroelectric Memory Device

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