Nanoepitaxy of GaAs on a Si(001) substrate using a round-hole nanopatterned SiO₂mask

Abstract

GaAs is grown by metal-organic vapor-phase epitaxy on a 55 nm round-hole patterned Si substrate with SiO2 as a mask. The threading dislocations, which are stacked on the lowest energy facet plane, move along the SiO2 walls, reducing the number of dislocations. The etching pit density of GaAs on the 55 nm round-hole patterned Si substrate is about 3.3 × 105 cm−2. Compared with the full width at half maximum measurement from x-ray diffraction and photoluminescence spectra of GaAs on a planar Si(001) substrate, those of GaAs on the 55 nm round-hole patterned Si substrate are reduced by 39.6 and 31.4%, respectively. The improvement in material quality is verified by transmission electron microscopy, field-emission scanning electron microscopy, Hall measurements, Raman spectroscopy, photoluminescence, and x-ray diffraction studies.

Epitaxial growth of highly mismatched III-V materials on (001) silicon for electronics and optoelectronics

“…In direct GaAs-on-Si epitaxy with an abrupt transition from the substrate to the overgrown GaAs, a two-step method [30] is widely adopted to improve the structural perfection of the hetero-epitaxial thin ilms. Post-growth thermal cycle annealing [40][41][42], by which an epilayer is subjected to large temperature oscillations and thus periodically switching between compressed and tensile states [43], has been found effective in reducing threading dislocation densities. Insertion of dislocation ilter layers, such as a strained layer superlattice [44] or thin strained layers [45], can facilitate the annihilation of threading dislocations thereby minimize intrusion of dislocations in the active layers of interest.…”

Epitaxial growth of antiphase boundary free GaAs layer on 300 mm Si(001) substrate by metalorganic chemical vapour deposition with high mobility

“…The first challenge is the lattice mismatch between silicon and gallium arsenide (4.1%), which induces the formation of crystalline defects to accommodate the strain in the material. To reduce crystalline defects density, various smart improvements have been investigated like post-growth thermal cycle annealing, 2,8 insertion of dislocation filter layer, 9 selective growth in trenches using aspect ratio trapping (ART) method [10][11][12] or Ge/GeSi buffer layer. 13 The second challenge is the difference of thermal expansion coefficients between Si and III-V (6.6 × 10 −6 K −1 and 2.3 × 10 −6 K −1 for GaAs and Si, respectively), which limits the film thickness before crack appears.…”

Heteroepitaxy of III–V Zinc Blende Semiconductors on Nanopatterned Substrates

“…resulting for a GaAs top layer thickness of 1 μm [54] still exceeds the value achieved with ART growth of GaAs using a SiO 2 cylinder hole mask [48] (Section 2.1.3.2).…”

“…Despite this benefit, ART with cylinder hole masks has been investigated only by few research groups [48][49][50]. Hsu et al [48] reported the MOVPE growth of smooth continuous 900 nm thick GaAs layers of low defect density on Si(001) substrate patterned with a round nanohole SiO 2 mask having a hole diameter of 55 nm and aspect ratio of 4.7. Like in the case of ART trenches, threading misfit defects were confined to the lower part of the holes, giving monocrystalline, relaxed GaAs in the upper part and a very low etch pit density of 3.3 × 10 5 cm…”

“…Application of a two-stage growth scheme (nucleation layer at low temperature, main growth at higher temperature) allowed to avoid thermal tensile strains in GaAs arising from the thermal expansion mismatch between Si and GaAs, as observed in GaAs layers on planar Si substrates by a redshift of the photoluminescence bandgap emission energy. However, the surface morphology of the coalesced GaAs layer and its defect structure above the SiO 2 holes has not been addressed in the work of Hsu et al [48].…”