Nanoimprint edge placement error elements and control

Establishing a nanoimprint lithography ecosystem

“…To be an effective solution for the fabrication of advanced devices, the NIL process must be compatible with pattern transfer methods needed to etch into underlying layers. To optimize critical dimension uniformity both locally and globally, as well as minimize linewidth roughness after etch, a Direct Current Superposition (DCS) function was introduced last year 19 to enable the pattern transfer of a multilayer resist stack and smooth the features after etch, as shown in Figures 9 and 10. The resultant process enabled an edge placement error (EPE) tolerance of less than 8nm and methods to further reduce EPE to 6nm were also proposed.…”