Nanoscale channel engineered double gate MOSFET for mixed signal applications using high‐k dielectric

Nirmal, D.; Vijayakumar, P.; Shruti, K; Mohankumar, N.

doi:10.1002/cta.1800

Cited by 18 publications

(3 citation statements)

References 19 publications

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“…This adverse threshold voltage roll-off effect is the most daunting road block in future MOSFET design. The minimum acceptable channel length is primarily determined by this roll-off [42]- [43], [76]. So here we introduce channel and gate engineering techniques into the FinFETs to reduce subthreshold leakage current and SCE.…”

Section: Channel and Gate Engineered Finfetsmentioning

confidence: 99%

A Review of Nanoscale Channel and Gate Engineered FINFETs for VLSI Mixed Signal Applications Using Zirconium - di - Oxide Dielectrics

Nirmal¹,

Kumar²,

Shruti³

et al. 2014

JESTR

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In the past, most of the research and development efforts in the area of CMOS and IC's are oriented towards reducing the power and increasing the gain of the circuits. While focusing the attention on low power and high gain in the device, the materials of the device also been taken into consideration. In the present technology, Computationally intensive devices with low power dissipation and high gain are becoming a critical application domain. Several factors have contributed to this paradigm shift. The primary driving factor being the increase in scale of integration, the chip has to accommodate smaller and faster transistors than their predecessors. During the last decade semiconductor technology has been led by conventional scaling. Scaling, has been aimed towards higher speed, lower power and higher density of the semiconductor devices. However, as scaling approached its physical limits, it has become more difficult and challenging for fabrication industry. Therefore, tremendous research has been carried out to investigate the alternatives, and this led to the introduction of new Nano materials and concepts to overcome the difficulties in the device fabrications. In order to reduce the leakage current and parasitic capacitance in devices, gate oxide high-k dielectric materials are explored. Among the different high-k materials available the nano size Zirconium dioxide material is suggested as an alternate gate oxide material for devices due to its thermal stability and small grain size of material. To meet the requirements of ITRS roadmap 2012, the Multi gate devices are considered to be one of the most promising technologies for the future microelectronics industry due to its excellent immunity to short channel effects and high value of On current. The double gate or multi gate devices provide a better scalability option due to its excellent immunity to short-channel effects. Here the different high-k materials are replaced in different Multi Gate MOSFET devices and its performance were studied.

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Section: Channel and Gate Engineered Finfetsmentioning

confidence: 99%

A Review of Nanoscale Channel and Gate Engineered FINFETs for VLSI Mixed Signal Applications Using Zirconium - di - Oxide Dielectrics

Nirmal¹,

Kumar²,

Shruti³

et al. 2014

JESTR

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“…It is worth mentioning that, the conventional multilevel inverters have borne high switching elements such as: switches, capacitors, diodes and the suchlike toward producing high step number. Over the past several years, many different structures and technologies based on IJBT and MOSFET semiconductors with have been introduced [18,19,20,21].…”

Section: Introductionmentioning

confidence: 99%

Novel harmonic elimination strategy based on Multi-Objective Grey Wolf Optimizer to ameliorate voltage quality of odd-nary multi-level structure

Falehi

2020

Heliyon

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In this paper, a novel Asymmetrical Multi-Level Inverter (AMLI) is suggested to solve the voltage quality problem. The suggested AMLI has been constructed based on series connection of sub-AMLIs to create a high-step quasisinusoidal voltage with considering few semiconductor switches. The ladder capacitors of sub-AMLI have been clamped to the H-bridge structure via several bi-directional switches. Based on an innovative geometric progression for DC power supplies of AMLI, it can operate as so-called odd-nary AMLI. It has effectually created a quasi-sinusoidal with high steps i.e., low Total Harmonic Distortion (THD) with respect to low number of switches. The performance of suggested AMLI has been thoroughly compared with other inventive asymmetrical and symmetrical multilevel inverters. Following that, scission-style harmonic elimination based on Pulse Width Modulation (PWM) is introduced to enhance voltage quality of AMLI. Three prominent criterions related to voltage quality i.e., desired fundamental component, elimination of third harmonic and reduction of THD have been assigned as objective functions of optimization problem. Considering the multi-objective nature of the optimization problem, non-dominated sorting Multi-Objective Grey Wolf Optimizer (MOGWO) has been implemented to solve the optimization problem, and then compared with Non-dominated Sorting Genetic Algorithm II (NSGA-II). To sum up, the relevant analytical studies along with both the simulation and experimental results have transparently validated the performance of suggested AMLI. Also, the voltage quality problem using MOGWO-based scission-style harmonic elimination strategy has been well approved.

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“…The improvements originate from the strong gate electrostatics control and lightly doped thin film body, respectively. In addition, using high‐ k gate dielectric further reduces the short channel effects and also gate leakage current .…”

Section: Introductionmentioning

confidence: 99%

A FinFET SRAM cell design with BTI robustness at high supply voltages and high yield at low supply voltages

Ebrahimi

Asadpour

Afzali-Kusha

et al. 2015

Circuit Theory & Apps

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Summary In this paper, a SRAM cell structure which uses pMOS access transistors and predischarged bitlines is presented. By using the strained pMOS transistor technology, the degradation of the read static noise margin (SNM) at high supply voltages due to the aging, especially in the presence of symmetric stress, is suppressed. In contrast to conventional cell, the write margin of the proposed cell does not degrade considerably at low supply voltages. To assess the efficacy, the proposed cell is compared with conventional cell for two cases of unstrained and strained pMOS. A comparative study is performed using mixed mode device/circuit simulations for a gate length of 22 nm. The results show that the read SNM degradation due to the symmetric aging at the supply voltage of 1 V is about 6% after three years for the proposed strained structure, while degradations are 14%, 12%, and 11% for the unstrained proposed structure, unstrained, and strained conventional structures, respectively. In addition, the proposed cell has both read and write cell sigma yields higher than six for supply voltages ranging from 1 V down to 0.5 V while the other structures have read or write yields less than six at the minimum supply voltage. Through some work function tuning, the cell sigma yields of the other structures reach above six for both read and write while being still lower than those of the proposed structure. Copyright © 2015 John Wiley & Sons, Ltd.

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Nanoscale channel engineered double gate MOSFET for mixed signal applications using high‐k dielectric

Cited by 18 publications

References 19 publications

A Review of Nanoscale Channel and Gate Engineered FINFETs for VLSI Mixed Signal Applications Using Zirconium - di - Oxide Dielectrics

A Review of Nanoscale Channel and Gate Engineered FINFETs for VLSI Mixed Signal Applications Using Zirconium - di - Oxide Dielectrics

Novel harmonic elimination strategy based on Multi-Objective Grey Wolf Optimizer to ameliorate voltage quality of odd-nary multi-level structure

A FinFET SRAM cell design with BTI robustness at high supply voltages and high yield at low supply voltages

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