Phase change memory cells were fabricated using plasma-enhanced cyclic chemical-vapor-deposited Ge 2 Sb 2 Te 5 ͑GST͒ thin films deposited on 300 nm diameter TiN/W contact plugs formed in a SiO 2 layer. A 2, 4, and 8 nm thick atomic deposited TiO 2 layer was interposed between the GST and underlayer containing the contact plug. The necessary reset current and power decreased with increasing the TiO 2 interlayer thickness. Adoption of the optimum thickness ͑4 nm͒ TiO 2 layer decreased the necessary reset power to ϳ45% of the cell without the TiO 2 layer. This was attributed mainly to the effective heat insulation by the 4 nm thick TiO 2 layer. The structural investigation and electrothermal simulation results for the fabricated cells showed a good match between the electrical performance and phase changed volume, which can explain the improvement in switching parameters of the proper TiO 2 layer interposed cell.Phase change random access memory ͑PCRAM͒ has attracted considerable interest recently for highly integrated nonvolatile memory ͑NVM͒ devices. 1-3 There are many major advantages of the PCRAM compared with conventional NVM, such as the NAND or NOR-type flash memory. In contrast to NAND flash, perfect random access during data writing and reading is possible, which allows effective cell use and rapid operation. Although NOR flash allows random access operation, the tunneling of electrons between the channel and floating gate to write and erase the data results in the need for a long writing time ͑from a few microseconds to milliseconds͒ and high voltage ͑15-20 V͒ in both NAND and NOR flashes. This is not the case for the PCRAM due to the rapid switching speed of phase change ͑PC͒ materials ͑Ͻ100 ns͒, typically Ge 2 Sb 2 Te 5 ͑GST͒, under the low applied voltage, Ͻ3 V. A reasonably small cell size of the PCRAM ͑6F 2 , where F is the minimum feature size͒ in a conventional 1 transistor-1 resistor configuration is another merit of this device although it is still slightly larger than that of NAND ͑ϳ5F 2 and ϳ10F 2 for the NAND and NOR, respectively͒. However, there are several drawbacks of the current PCRAMs. The high level of reset current ͑I reset ϳ 0.5 mA͒ needed to switch the GST material from a crystalline to amorphous state ͑reset process͒ has been the major obstacle to the further scaling of PCRAM because of the limited on-current drive capability of the cell transistor ͑Ͻ1 mA m −1 ͒. 4 Several methods have been used in an attempt to overcome this problem including doping of GST, 3-7 confining the GST into a contact plug, 8-10 adopting an ultrathin interface thermal barrier layer ͑UTB͒ of Ta 2 O 5 ͑Ref. 11͒, or TiO 2 , 12 and adopting diodes as the selection device that generally offers a larger drive current than the field-effect transistor. 3 Among them, adopting a UTB appears to be an effective method for reducing I reset , even though other methods also showed some improvements. It was suggested that the oxide layer with a lower thermal conductivity suppresses the heat loss to the metal plug and impro...