Nanoscale Three-Independent-Gate Transistors: Geometric TCAD Simulations at the 10 nm-Node

Cadareanu, Patsy; Gaillardon, Pierre-Emmanuel

doi:10.1109/nmdc47361.2019.9084015

Cited by 7 publications

(3 citation statements)

References 8 publications

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“…Although we focus on fairly large channel lengths for demonstration purposes the RFET concept is physically scalable, [54] recently scalability down to 10 nm nodes has been verified by device TCAD simulations. [55,56] Nevertheless, the structural sizes of RFETs are by far exceeding state-of-the-art CMOS MOSFETs. However, they allow a circuit design that significantly reduces the chip area for the same logic operation compared to standard CMOS technology.…”

Section: Resultsmentioning

confidence: 99%

Reconfigurable Complementary and Combinational Logic Based on Monolithic and Single‐Crystalline Al‐Si Heterostructures

Böckle

Sistani

Bažíková

et al. 2022

Adv Elect Materials

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Modern society is highly depending and relying on electronic computing devices, as for example, employed in efficient servers, personal computers, and mobiles, and currently being explored toward the realization of emerging computing paradigms, such as "artificial intelligence" and the "Internet of Things". [1] A key enabler for these paradigms is the complementary metal-oxide-semiconductor (CMOS) technology, which utilizes the concept of complementary n-and p-type field-effect transistors (FET) to construct Boolean logic gates. Importantly, in CMOS technology the logic functions are fixed by the physical layout of interconnects and the definition of doped regions and thus do not allow for a flexible alteration of the circuits after production. The continuous shrinking of feature sizes of these Si metal-oxide-semiconductor field-effect transistors (MOSFETs) has been providing performance enhancement and higher power efficiency throughout the last decades. However, classical scalability is limited [2] and the static nature of the MOSFET primitives was not developed to provide runtimeadaptability as required for new circuit paradigms. A concept to overcome the static nature in CMOS technology and reduce overall circuit area and power consumption are reconfigurable FETs (RFETs), [3][4][5] encompassing a broad family of devices that enable a reconfiguration of the dominant carrier type based on either Schottky-barrier field-effect transistors (SBFET), [4,[6][7][8][9] or steep slope band-to-band tunneling transistors (TFET), [10][11][12][13] capable of dynamically altering the device operation between n-and p-type. This device concept thus gives rise to a paradigm change where devices, circuits, and even systems are actively and dynamically reconfigured after manufacturing or, as particularly noteworthy, even during run-time, enabling an adaption to the needed logic function of a circuit. Importantly, this "fine-grain" approach is fundamentally different to the already available "coarse-grain" approach followed in field programmable gate arrays (FPGAs) [14] based on signal routing to predefined logic blocks, resulting in high latency in data Metal-semiconductor heterostructures providing geometrically reproducible and abrupt Schottky nanojunctions are highly anticipated for the realization of emerging electronic technologies. This specifically holds for reconfigurable field-effect transistors, capable of dynamically altering the operation mode between n-or p-type even during run-time. Targeting the enhancement of fabrication reproducibility and electrical balancing between operation modes, here a nanoscale Al-Si-Al nanowire heterostructure with single elementary, monocrystalline Al leads and sharp Schottky junctions is implemented. Utilizing a three top-gate architecture, reconfiguration on transistor level is enabled. Having devised symmetric on-currents as well as threshold voltages for n-and p-type operation as a necessary requirement to exploit complementary reconfigurable circuits, selected implementations of log...

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Section: Resultsmentioning

confidence: 99%

Reconfigurable Complementary and Combinational Logic Based on Monolithic and Single‐Crystalline Al‐Si Heterostructures

Böckle

Sistani

Bažíková

et al. 2022

Adv Elect Materials

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“…[23] In this respect, the overlap between the PGs and the source/drain regions is critical, as a small overlap is necessary to achieve a low off-state and ensure small parasitic capacitances. [39,23,40] Therefore, we expect significantly enhanced key performance parameters of our SiGe RFET utilizing shorter channel lengths and thinner effective gate oxide thicknesses. For a convenient comparison of the key parameters of the proposed SiGe RFET with SiO 2 and HfO 2 gate dielectric, Table 1 values of the ten best SiGe RFETs compared with Al-Si-based RFETs.…”

Section: Resultsmentioning

confidence: 99%

Reconfigurable Field‐Effect Transistor Technology via Heterogeneous Integration of SiGe with Crystalline Al Contacts

Fuchsberger

Wind

Sistani

et al. 2023

Adv Elect Materials

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Reconfigurable field‐effect transistors, capable of being dynamically programmed during run‐time, overcome the static nature of conventional complementary metal‐oxide semiconductors by reducing the transistor count and the circuit path delay. Thereby, SiGe and Ge are predicted to boost drive currents, switching speed and to reduce power consumption. Nevertheless, Ge‐based reconfigurable field‐effect transistor prototypes have so far fallen short in reaching both the promised performance due to interface instability to their contacts and gate oxides, as well as in reaching the current–voltage symmetry necessary for circuit applicability. Here, a top‐down fabricated SiGe‐based reconfigurable transistor technology is reported that is comprised of a vertical Si‐Si0.67Ge0.33 heterostructure enabling the envisioned high and symmetric on‐currents of both n‐ and p‐type operation. Monolithic integration with single‐elementary crystalline Al contacts alleviates process variability compared to conventional Ni‐silicide/Ni‐germanide contacts and introduces an ultra‐thin Si interlayer providing stability and equal injection efficiency of holes and electrons. The implementation of a three top‐gate transistor in combination with a hysteresis‐free Si/SiO2/HfO2 gate stack enhances polarity control and leakage current suppression to limit static power dissipation. Importantly, the obtained Al‐Si‐SiGe multi‐heterojunction and advanced reconfigurable transistor design is the first Ge‐based technology showing the envisioned stability and performance enhancements.

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“…Thanks to the Schottky barrier cutoff, IOFF is extremely low at 3.3 nA/μm and 0.1 nA/μm for n-and p-type operation respectively. Further work and discussion of this simulation is available in [28]. These current drives are approximately 10 X lower than the previous 22 nm TIGFET device simulations [7] which used a supply voltage of 1.2 V. This loss is primarily due to the 0.7 V supply voltage used in the 10 nm devices as is standard for technology at this node.…”

Section: Device Tcad Workmentioning

confidence: 97%

A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors

Cadareanu¹,

Gore²,

Giacomin³

et al. 2020

IFIP Advances in Information and Communication Technology

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The Three-Independent-Gate Field-Effect Transistor (TIGFET) is a promising beyond-CMOS technology which offers multiple modes of operation enabling unique capabilities such as the dynamic control of the device polarity and dual-threshold voltage characteristics. These operations can be used to reduce the number of transistors required for logic implementation resulting in compact logic designs and reductions in chip area and leakage current.However, the evaluation of TIGFET-based design currently relies on a close approximation for the Power, Performance, and Area (PPA) rather than traditional layout-based methods. To allow for a systematic evaluation of the design area, we present here a publicly available Predictive Process Design Kit (PDK) for a 10 nm-diameter silicon-nanowire TIGFET device. This work consists of a SPICE model and full custom physical design files including a Design Rule Manual, a Design Rule Check, and Layout Versus Schematic decks for Calibre®. We validate the design rules through the implementation of basic logic gates and a full-adder and compare extracted metrics with the FreePDK15nm TM PDK. We show 26% and 41% area reduction in the case of an XOR gate and a 1-bit fulladder design respectively. Applications for this PDK with respect to hardware security benefits are supported through a differential power analysis study.

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Nanoscale Three-Independent-Gate Transistors: Geometric TCAD Simulations at the 10 nm-Node

Cited by 7 publications

References 8 publications

Reconfigurable Complementary and Combinational Logic Based on Monolithic and Single‐Crystalline Al‐Si Heterostructures

Reconfigurable Complementary and Combinational Logic Based on Monolithic and Single‐Crystalline Al‐Si Heterostructures

Reconfigurable Field‐Effect Transistor Technology via Heterogeneous Integration of SiGe with Crystalline Al Contacts

A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors

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