Nanosecond Delay Floating High Voltage Level Shifters in a 0.35 $\mu$m HV-CMOS Technology

Abstract

We present novel circuits for high-voltage digital level shifting with zero static power consumption. The conventional topology is analysed, showing the strong dependence of speed and dynamic power on circuit area. Novel techniques are shown to circumvent this and speed up the operation of the conventional level-shifter architecture by a factor of 5-10 typically and 30-190 in the worst case. In addition, these circuits use 50% less silicon area and exhibit a factor of 20-80 lower dynamic power consumption typically. Design guidelines and equations are given to make the design robust over process corners, ensuring good production yield. The circuits were fabricated in a 0.35 m high-voltage CMOS process and verified. Due to power and IO speed limitation on the test chip, a special ring oscillator and divider structure was used to measure inherent circuit speed.

A Novel Low Delay High-Voltage Level Shifter with Transient Performance Insensitive to Parasitic Capacitance and Transfer Voltage Level

“…The inverse Schmitt trigger uses transistor configuration of Table 2. To evaluate the overall performance of the proposed HVLS, the figure of merit (FoM) [17] is used as a benchmark, which takes into consideration of transfer delay, process note length and transfer voltage.…”

“…It is widely used in multi-rail power supply on-chip systems, such as Very Large Scale Integration circuit (VLSI), Micro-Electro-Mechanical Systems (MEMS), mixed-signal integrated circuits and power-conversion systems [1][2][3][4][5][6][7][9][10][11][14][15][16][17][18][20][21][22][24][25][26].…”

“…For high voltage applications [4][5][6][7]11,[14][15][16][17]18,22,24], the recent years growing markets in smart electronic vehicles, renewable energy systems, high-brightness LED lighting systems, and MEMS MOSFETs have advantages of significantly lower on-resistance and threshold voltage than those of the thick-oxide devices [22]. However, the thin-oxide high-voltage MOSFETs have limitations on VGS (voltage difference from gate to source terminals of transistor) swing.…”

“…However, clamping structure introduces additional parasitic capacitance which will adversely affect the transfer response of HVLS. This problem gets worse as transfer voltage level increases [17].…”

Design of a Low-power CMOS Level Shifter for Low-delay SoCs in Silterra 0.13 µm CMOS Process

“…But to get higher voltage from a low voltage supply domain in LS circuits, complicated circuit architectures are required. In order to design a simple LS circuit, proper design techniques must be utilized to balance the units of the circuit functioning at the high power supply voltage (VDDH) level with the input unit driving capability of the Level shifter [9] [15].…”