We present novel circuits for high-voltage digital level shifting with zero static power consumption. The conventional topology is analysed, showing the strong dependence of speed and dynamic power on circuit area. Novel techniques are shown to circumvent this and speed up the operation of the conventional level-shifter architecture by a factor of 5-10 typically and 30-190 in the worst case. In addition, these circuits use 50% less silicon area and exhibit a factor of 20-80 lower dynamic power consumption typically. Design guidelines and equations are given to make the design robust over process corners, ensuring good production yield. The circuits were fabricated in a 0.35 m high-voltage CMOS process and verified. Due to power and IO speed limitation on the test chip, a special ring oscillator and divider structure was used to measure inherent circuit speed.

The development of high-voltage-enabling techniques in deepsubmicron CMOS technologies has recently increased in importance. The growing integration density of VLSI circuits and the low-power requirements of complex signal processing applications, drives the use of deep-submicron technologies in modern ICs. Since these technologies imply low supply voltages [1] there is no headroom for the design of analog circuits as oxide breakdown and hot carrier effects arise. Moreover, since the VLSI circuits are optimized for speed, minimum power consumption and maximum integration density, the power supply needs to decrease. In this way the requirements of system applications where high-voltage capabilities are needed cannot be achieved.High-voltage-enabling techniques in deep-submicron technologies offer a solution to this problem. However, mainly the choice to change the technology is made to cope with the voltage specifications. Currently, the major research effort is in the reduction of extra mask-sets and/or technology steps in which the additional devices like bipolar or DMOS-transistors are created.The presented high-voltage output driver in standard CMOS uses alternative circuit topologies and drain-source engineering. These techniques allow the driver to operate at a higher supply voltage than the nominal supply voltage within the limits of the design rules of a mainstream CMOS technology. This ensures at least the same nominal lifetime of the high-voltage output driver as described by the electrical design rules of the used technology, without extra mask steps. The driver uses a minimum number of stacked transistors to cope with the high supply voltage. This is a great advantage in terms of area compared to a previous published high-voltage output driver in standard CMOS [2]. The more stacked transistors needed, the larger the area becomes since the on-resistance is determined by the width and the number of stacked transistors.This design uses dynamic bias voltage circuits to set the correct gate voltages of the stacked output transistors during operation. Figure 7.8.1 depicts the block diagram of the presented driver. In order to get the correct bias voltage, information from the output is fed back into the bias voltage circuits. One can distinguish three major parts: a levelshifter, a p-switch block and its complementary n-switch block. The p-and n-switch blocks consist of the dynamic bias voltage circuits, the output stacked transistors and a tapered buffer. Unlike [2] the stacked transistors are either in the cut-off or the triode region. This means that the supply voltage of the driver can be as high as the number of stacked transistors used per switch block multiplied by their nominal supply voltage. Figure 7.8.2 depicts the schematic of the n-switch block with the dynamic bias voltage circuit of the designed driver in more detail. The p-switch block is its complement. The driver consists of 3 stacked transistors per switch block. This corresponds to a supply voltage of 3 times the nominal supply voltage. ...

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