Highly efficient xDSL line drivers in 0.35-μm CMOS using a self-oscillating power amplifier

Piessens, Tim; Steyaert, Michiel

doi:10.1109/jssc.2002.806276

Cited by 24 publications

(15 citation statements)

References 3 publications

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“…In reality however, other noise sources coming from the modulator and the TDC contribute also to errors in the A/D conversion, so their effect must be kept lower than that of the quantization noise generated from the TDC. Since ADSMs are thoroughly analyzed in [3], [6], [7], the main foucus in this section will go to the TDC and the demodulator. All simulations are done in Matlab.…”

Section: Systemmentioning

confidence: 99%

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A/D conversion using an Asynchronous Delta-Sigma Modulator and a time-to-digital converter

Daniels

Dehaene

Steyaert

et al. 2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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An analog to digital conversion scheme based on an Asynchronous ΔΣ Modulator is presented. It uses a Time-to-Digital converter to convert the continuous-time square wave signal produced by the Asynchronous ΔΣ Modulator to a time-quantized digital signal. The original input signal is then recovered by applying a digital demodulation algorithm derived from general duty-cycle modulation theory. This technique shifts the complexity towards the digital domain and is therefore especially suited for ultra-low voltage technologies beyond 90 nm. Simulations show 13 bit accuracy for Bluetooth baseband 500 kHz with a first-order ΔΣ modulator and a Time-to-Digital Converter with 10 ps resolution running at 12 MHz. Using a second-order feedback system to shape the quantization noise of the Time-to-Digital converter, the bandwidth can be increased to 12 MHz with 12 bit accuracy, suitable for video applications.

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Section: Systemmentioning

confidence: 99%

“…6. The digital output of the demodulator is converted to an analog signal with a multibit D/A Converter and Without noise shaping, the SNDR is reduced by 10 dB/decade of increasing F , see (7). However, noise shaping theoretically increases the SNDR by 20N dB/decade with N the order of the noise shaping filter.…”

Section: Noise Shapingmentioning

confidence: 99%

A/D conversion using an Asynchronous Delta-Sigma Modulator and a time-to-digital converter

Daniels

Dehaene

Steyaert

et al. 2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…3,[13][14][15] Because of this property, the APWM modulators have attracted a lot of attention for having an excellent SNR performance controller and they can be applied to convert a single-bit signal into a PWM signal which usually used in the control loop of the several power converting circuit. For example, they can be employed in inverter circuits, active filters, 14 class-D amplifiers, 16 Universal Mobile Transmitter Systems (UMTS), 17 ADSL/VDSL line drivers, 18,19 etc. Unfortunately, the precise mathematical analysis of the APWMs is a demanding task due to the nonlinearity of the system.…”

Section: Introductionmentioning

confidence: 99%

An asynchronous pulse width modulator for DC‐DC buck converter

Inanlou

Shoaei

Tamaddon

2019

Circuit Theory & Apps

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Summary This paper presents an asynchronous pulse width modulation (APWM) approach for the analysis of a new class of the switched mode power supply (SMPS). The proposed APWM significantly simplified the mathematical analysis by utilizing a binary comparator (BAPWM) and a distinctive delay cell instead of hysteretic comparator. By this way, the mathematical analysis can be extended to study the behavior of high‐order self‐oscillating modulators in terms of key parameters such as the harmonic distortion and the stability. The performance of the proposed BAPWM is deeply analyzed for different orders of loop filters (here up to third order) in both time and frequency domain. To verify the effectiveness of the proposed analytical derivations, the BAPWMs are employed in a classic synchronous DC‐DC buck converter and its closed loop performance, in terms of stability, has been investigated. Then the converter is designed and simulated in 130‐nm CMOS technology to convert input voltage of 5 to 3.3 V with maximum load current of 1 A, using Spectre simulator. From the post‐layout simulation results, the peak efficiency conversion efficiency for 3.3 V output voltage is higher than 89%.

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“…Class D amplifiers have improved the efficiency of audio and xDSL power amplifiers in the past years [1], [2]. In most of these applications the analog signal comes from a digital sampled source, which is then converted into an analog signal by means of a DAC, followed by an analog Pulse Width Modulator (PWM).…”

Section: Introductionmentioning

confidence: 99%

A time encoded decimation filter for noise shaped power DACs

Hernández

Fernández

Prefasi

et al. 2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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This paper presents a new approach to reduce the out of band energy in a class D amplifier driven by a DAC. The proposed architecture is based on a Time Encoded Filter (TEF). The TEF operates as a discrete time linear system on the pulse widths of a PWM signal rather than on the amplitudes of a sequence. It only requires RC circuits, comparators and digital logic. Hence, it can be integrated along with the D/A converter. The main advantage of this approach is that the number of power inductors and capacitors of the off chip low pass filter may be reduced.

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Highly efficient xDSL line drivers in 0.35-μm CMOS using a self-oscillating power amplifier

Cited by 24 publications

References 3 publications

A/D conversion using an Asynchronous Delta-Sigma Modulator and a time-to-digital converter

A/D conversion using an Asynchronous Delta-Sigma Modulator and a time-to-digital converter

An asynchronous pulse width modulator for DC‐DC buck converter

A time encoded decimation filter for noise shaped power DACs

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