The development of high-voltage-enabling techniques in deepsubmicron CMOS technologies has recently increased in importance. The growing integration density of VLSI circuits and the low-power requirements of complex signal processing applications, drives the use of deep-submicron technologies in modern ICs. Since these technologies imply low supply voltages [1] there is no headroom for the design of analog circuits as oxide breakdown and hot carrier effects arise. Moreover, since the VLSI circuits are optimized for speed, minimum power consumption and maximum integration density, the power supply needs to decrease. In this way the requirements of system applications where high-voltage capabilities are needed cannot be achieved.High-voltage-enabling techniques in deep-submicron technologies offer a solution to this problem. However, mainly the choice to change the technology is made to cope with the voltage specifications. Currently, the major research effort is in the reduction of extra mask-sets and/or technology steps in which the additional devices like bipolar or DMOS-transistors are created.The presented high-voltage output driver in standard CMOS uses alternative circuit topologies and drain-source engineering. These techniques allow the driver to operate at a higher supply voltage than the nominal supply voltage within the limits of the design rules of a mainstream CMOS technology. This ensures at least the same nominal lifetime of the high-voltage output driver as described by the electrical design rules of the used technology, without extra mask steps. The driver uses a minimum number of stacked transistors to cope with the high supply voltage. This is a great advantage in terms of area compared to a previous published high-voltage output driver in standard CMOS [2]. The more stacked transistors needed, the larger the area becomes since the on-resistance is determined by the width and the number of stacked transistors.This design uses dynamic bias voltage circuits to set the correct gate voltages of the stacked output transistors during operation. Figure 7.8.1 depicts the block diagram of the presented driver. In order to get the correct bias voltage, information from the output is fed back into the bias voltage circuits. One can distinguish three major parts: a levelshifter, a p-switch block and its complementary n-switch block. The p-and n-switch blocks consist of the dynamic bias voltage circuits, the output stacked transistors and a tapered buffer. Unlike [2] the stacked transistors are either in the cut-off or the triode region. This means that the supply voltage of the driver can be as high as the number of stacked transistors used per switch block multiplied by their nominal supply voltage. Figure 7.8.2 depicts the schematic of the n-switch block with the dynamic bias voltage circuit of the designed driver in more detail. The p-switch block is its complement. The driver consists of 3 stacked transistors per switch block. This corresponds to a supply voltage of 3 times the nominal supply voltage. ...

The persistent growing demand for broadband internet has triggered the telephone companies to improve the xDSL standards to bridge the last mile between the central office (CO) and the end user. The aDSL2+ standard doubles the bandwidth of an aDSL system to 2.2MHz and hence increases the bit rate up to 24Mb/s. The high crest factor (CF) of discrete multi-tone (DMT) modulated signals poses serious problems for an efficient and low-cost implementation of the line driver [1]. In the nano-electronic era, the line driver remains more than ever the major bottleneck for lowering the cost and power. The low supply voltages coming from nanometer technologies increase the current density in the line driver. Together with the high CF and the doubled bandwidth, a highly efficient aDSL2+ line driver in a low-voltage, lowcost CMOS technology seems to be a contradiction.The aDSL2+ line driver presented here is a self oscillating power amplifier (SOPA) with a high-voltage output buffer in standard 1.2V 0.13µm CMOS. A SOPA line driver can be quite successful in sub-micrometer technologies, since it can drive DMT signals with a high CF efficiently [2]. But, as with any power amplifier, its efficiency and reliability drop with decreasing supply voltage. An aDSL2+ system delivers an average of 20dBm to a 100Ω twisted-pair line. Lowering the supply voltage thus results in an increased current density for a constant output power. This in turn increases hot carrier generation and electro-migration, both of which affect the reliability of the driver. The large current also results in a drop in efficiency because of the increased switching and conduction losses of the driver. Moreover, the large CF causes the driver to put signals with a high voltage-swing on the line. Since the output voltage-swing of the driver is limited by its supply voltage, a transformer with a high turns-ratio has to be used. The large return signal attenuation then limits the practical use of the line driver.To overcome these low-voltage issues, a high-voltage output buffer is included in the SOPA architecture. The high-voltage buffer is, like all the building blocks in this line driver, designed in a standard, submicron CMOS technology. Therefore, it is demonstrated that the use of extra mask sets to create high-voltage devices, such as LDMOS or thick-oxide transistors, can be avoided. This simplicity makes this line driver very attractive in terms of cost and the prospects for integration. Figure 29.4.1 shows the block diagram of the line driver. The single SOPA comprises a continuous-time RC integrator followed by a non-clocked comparator. The SOPA is thus an asynchronous switching-type amplifier. The high-voltage buffer converts the output of the comparator to high voltage levels. The output of this buffer is fed back to the integrator using a loop filter. Since the integrator and comparator operate at the low, nominal supply voltage of the technology, the output of this buffer needs to be down converted within the voltage limits of the technology. This down ...

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The design of a high speed, low voltage to high voltage level shifter in a digital 1.2 V, 0.13 lm CMOS technology is presented. The topology uses two differentially switched cascoded transistor ladders. The output signal has an offset of two times the nominal supply voltage of the used technology with respect to the input signal. Oxide stress and hot carrier degradation is minimized since all transistors of the level shifter operate within the voltage limits imposed by the design rules of a mainstream CMOS technology.

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