High Voltage xDSL Line Drivers in Nanometer Technologies

Serneels, Bert; Steyaert, Michiel; Dehaene, Wim

doi:10.1007/978-1-4020-8263-4_10

Cited by 7 publications

(10 citation statements)

References 4 publications

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“…(2) and (7) respectively. Figure 12 shows the output and the drain current of this work (A) in comparison to previous work B ( Serneels and Steyaert, 2008) with a supply voltage of 4 V. In the previous work, the gate voltages of the second nMOS and pMOS transistors of a 2-stacked CMOS driver are fixed to the high level of the input signal. The principle of the work B is applied on a 2-stack CMOS driver in 65 nm technology with a nominal voltage of the I/O devices of 2.5 V. The comparison between the results of the rise/fall time and on-resistance of both works with different supply voltages (3.5, 4, 4.5 and 5 V) are given in Table 2.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…Thus one common method to design high-voltage circuits is to use highvoltage transistors, which are technology dependent (Bandyopadhyay et al, 2011). In contrast, high-voltage circuits based on stacked low-voltage CMOS transistors are more efficient because of their full compatibility with scaled technologies (Serneels and Steyaert, 2008;Nam et al, 2012;Bradburn and Hess, 2010).…”

Section: Introductionmentioning

confidence: 99%

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High-voltage circuits for power management on 65 nm CMOS

Pashmineh

Killat

2015

Adv. Radio Sci.

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Abstract. This paper presents two high-voltage circuits used in power management, a switching driver for buck converter with optimized on-resistance and a low dropout (LDO) voltage regulator with 2-stacked pMOS pass devices. The circuit design is based on stacked MOSFETs, thus the circuits are technology independent.High-voltage drivers with stacked devices suffer from slow switching characteristics. In this paper, a new concept to adjust gate voltages of stacked transistors is introduced for reduction of on-resistance. According to the theory, a circuit is proposed that drives 2 stacked transistors of a driver. Simulation results show a reduction of the on-resistance between 27 and 86 % and a reduction of rise and fall times between 16 and 83 % with a load capacitance of 150 pF at various supply voltages, compared to previous work. The concept can be applied to each high-voltage driver that is based on a number (N) of stacked transistors.The high voltage compatibility of the low drop-out voltage regulator (LDO) is established by a 2-stacked pMOS transistors as pass device controlled by two regulators: an error amplifier and a 2nd amplifier adjusting the division of the voltages between the two pass transistors. A high GBW and good DC accuracy in line and load regulation is achieved by using 3-stage error amplifiers. To improve stability, two feedback loops are utilized.In this paper, the 2.5 V I/O transistors of the TSMC 65 nm CMOS technology are used for the circuit design.

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

High-voltage circuits for power management on 65 nm CMOS

Pashmineh

Killat

2015

Adv. Radio Sci.

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“…Our focus is on the first two approaches, as we a) model the power consumption of an energy-efficient LD type, and b) study energy-efficient DSM based on derived LD power consumption models, leading to lowered transmit rates. We refer to [20,21] for an introduction to LD design for DSL and to [1,[22][23][24][25] for an overview of various energy saving techniques for DSL.…”

Section: Energy-efficiency In Dslmentioning

confidence: 99%

“…We generated numerous problem instances of (16) and (17) by setting H 21 c and H 12 c to all combinations out of the set {−90, −67.5, −45, −22.5, 0}dB, and for each of these combinations forming all target-rate combinations sampling the users' possible rates at 20 equi-distant rate-levels from 0 to the maximum achievable rate (i.e., 400 ratecombinations) d . After running successive GP for the problems in (16) and (17) we re-initialize the algorithm with the obtained result for the respective other problem and keep the best solution found for each problem e .…”

Section: Dsm Based On Successive Sinr-approximation and Geometric Promentioning

confidence: 99%

“…Searching for these weights is in fact the idea behind the projected gradient heuristic indicated in Section 'Analysis of the optimization problems in (16) and (17)' . With a decreasing parameter H 21 1 the needed sum-powers for constant target-rates decrease, leading to a decrease of the achievable gain ξ by LD power optimization compared to TP minimization, cf. Figure 7.…”

Section: Global Solutions Of Non-convex Ld Power Optimization Problemmentioning

confidence: 99%

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Modeling and optimization of the line-driver power consumption in xDSL systems

Wolkerstorfer

Trautmann

Nordström

et al. 2012

EURASIP J. Adv. Signal Process.

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Optimization of the power spectrum alleviates the crosstalk noise in digital subscriber lines (DSL) and thereby reduces their power consumption at present. In order to truly assess the DSL system power consumption, this article presents realistic line driver (LD) power consumption models. These are applicable to any DSL system and extend previous models by parameterizing various circuit-level non-idealities. Based on the model of a class-AB LD we analyze the multi-user power spectrum optimization problem and propose novel algorithms for its global or approximate solution. The thereby obtained simulation results support our claim that this problem can be simplified with negligible performance loss by neglecting the LD model. This motivates the usage of established spectral optimization algorithms, which are shown to significantly reduce the LD power consumption compared to static spectrum management.

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Enhancing the performances of recycling folded cascode OpAmp in nanoscale CMOS through voltage supply doubling and design for reliability

Mak

Liu

Zhao

et al. 2012

Circuit Theory & Apps

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Current-oriented operational amplifier (OpAmp) design has been common for its orderly current-to-speed tradeoff. However, for high-precision or high-linearity applications, increasing the current does not help much, as the supply voltage (V DD ) and intrinsic gain of the MOSFETs in ultra-scaled CMOS technologies are very limited. This paper introduces voltage-oriented circuit techniques to address such limitations. Specifically, a 2xV DD -enabled recycling folded cascade (RFC) OpAmp is proposed. It features: (1) current recycling to enhance the effective trans conductance by 4x with no extra power; (2) transistor stacking to boost the output resistance by one to two orders of magnitude; and (3) V DD elevating to enlarge the linear output swing by 4x. Comparing with its 1xV DD RFC and FC counterparts, the proposed solution achieves 20-dB higher DC gain (i.e. 72.8 dB) in open loop and 20-dB lower IM3 (i.e., -76.5 dB) in closed loop, under the same power budget of 0.6 mW in a 1-V General Purpose 65-nm CMOS process. In many applications, these joint improvements in a single stage are already adequate, being more power efficient (i.e. less current paths), stable (i.e. more phase margin), and compact (i.e. no frequency compensation) than multi-stage OpAmps. Voltage-conscious biasing and node-voltage trajectory check ensure the device reliability in both transient and steady states. No specialized high-voltage device is necessary.

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High Voltage xDSL Line Drivers in Nanometer Technologies

Cited by 7 publications

References 4 publications

High-voltage circuits for power management on 65 nm CMOS

High-voltage circuits for power management on 65 nm CMOS

Modeling and optimization of the line-driver power consumption in xDSL systems

Enhancing the performances of recycling folded cascode OpAmp in nanoscale CMOS through voltage supply doubling and design for reliability

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