A high speed, low voltage to high voltage level shifter in standard 1.2 V 0.13 μm CMOS

Serneels, Bert; Steyaert, Michiel; Dehaene, Wim

doi:10.1007/s10470-008-9156-y

Cited by 18 publications

(11 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This matches the device sizing decision made in Section II-A whereby the source voltage of the PDMOS is pulled down to at least initially. This improvement is not novel and has been used by others [12], [13]. However, we present a full analysis of, and design guidelines for, the technique for the first time.…”

Section: A Improvement I -Clampingmentioning

confidence: 99%

“…It is common practice to place low voltage (LV) circuitry in these floating wells and communicate between the various voltage domains via DMOS cascodes, particularly for digital control signals. Various techniques have been described in the literature [1]- [12]. While these designs are useful for their applications, they have disadvantages, as shown in Table II: 1) Low switching speed [1], [2]: This is due to the high gate and drain capacitances of DMOS transistors or the delay through a LV transistor stack 2) Large silicon area [1], [2], : This is due to the inability to share floating N-wells among PDMOS transistors or the large area of a LV transistor stack 3) Static power consumption [3]- [9]: Not suitable for batterypowered (especially implantable) applications 4) Dynamic control signals [4], [10]: This increases system complexity, especially for arrays of level shifters 5) High voltage capacitors [11], [12]: In many processes, HV capacitors can be constructed only with normal routing metals (overlap or finger arrangement), requiring large area to obtain reasonable capacitance values The novel techniques in this paper avoid the above drawbacks while simultaneously improving silicon area, speed and dynamic power consumption.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Nanosecond Delay Floating High Voltage Level Shifters in a 0.35 $\mu$m HV-CMOS Technology

Moghe¹,

Lehmann

Piessens³

2011

IEEE J. Solid-State Circuits

134

View full text Add to dashboard Cite

We present novel circuits for high-voltage digital level shifting with zero static power consumption. The conventional topology is analysed, showing the strong dependence of speed and dynamic power on circuit area. Novel techniques are shown to circumvent this and speed up the operation of the conventional level-shifter architecture by a factor of 5-10 typically and 30-190 in the worst case. In addition, these circuits use 50% less silicon area and exhibit a factor of 20-80 lower dynamic power consumption typically. Design guidelines and equations are given to make the design robust over process corners, ensuring good production yield. The circuits were fabricated in a 0.35 m high-voltage CMOS process and verified. Due to power and IO speed limitation on the test chip, a special ring oscillator and divider structure was used to measure inherent circuit speed.

show abstract

Section: A Improvement I -Clampingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Nanosecond Delay Floating High Voltage Level Shifters in a 0.35 $\mu$m HV-CMOS Technology

Moghe¹,

Lehmann

Piessens³

2011

IEEE J. Solid-State Circuits

134

View full text Add to dashboard Cite

show abstract

“…They are also composed of an inverter controlled by transmission gates and M 3,4 , which in turn are controlled by small logic circuits. Moreover, the drivers F 1 and G 2 feed two extra switches that make use of the stacking MOS technique [10] to protect the transistors. A CBT circuit is used to increase V G in order to reduce R ON of the transistors and enable the use of only an NMOS switch (without requiring a transmission gate).…”

Section: Switch Driversmentioning

confidence: 99%

Analysis and implementation of a power management unit with a multiratio switched capacitor DC–DC converter for a supercapacitor power supply

Madeira

Paulino

2016

Circuit Theory & Apps

View full text Add to dashboard Cite

An energy-harvesting system requires an energy-storing device to store the energy retrieved from the surrounding environment. Rechargeable batteries are commonly used to store this energy; however, because of the limited number of charge/discharge cycles, they need to be periodically replaced. A supercapacitor, which has, ideally, a limitless number of charge/discharge cycles, avoids this problem. In this case, it is required for the power management unit to produce a constant output voltage as the supercapacitor discharges. This paper presents a system with a multiratio switched capacitor DC-DC converter, in a 130-nm technology, with a maximum output power of 2 mW, a maximum efficiency of 79.63% and a maximum output ripple, in the steady state, of 23 mV for an input voltage range of 2.3-0.87 V. The proposed converter has four operation states, to maximize its efficiency, that correspond to the conversion ratios of 1/2, 2/3, 1/1 and 3/2. Its clock frequency is automatically adjusted to produce a stable output voltage of 1 V. These features are implemented through two distinct controller circuits that use two asynchronous time machines to dynamically adjust the clock frequency and to select the active state of the converter. All the theoretical expressions as well as the behaviour of the whole system were verified by using electrical simulations.When the transmission gate is on, the driver produces a complementary clock signal of ϕ 2 from V in to zero. When the transmission gate is off and M 3 is on, the inverter produces V in that turns off the switch. Figure 11. Transistors in the bold line are 3.3-V transistors, and those in the normal lines refer to 1.2-V transistors. PMOS and NMOS with undefined bulk have their bulk connected to V in /V out and ground respectively. 2028 R. MADEIRA AND N. PAULINO

show abstract

“…The conventional contention domain‐shifter employs a differential NMOS input pair with ratioed cross‐coupled PMOS pull‐up devices . The NMOS(s) in the input‐pair, when turned on, should be able to pull‐down their drain terminals by sinking more current than the respective PMOS load are sourcing to ensure state‐toggling.…”

Section: D2d Io Design Descriptionmentioning

confidence: 99%

IO circuit design for 2.5D through‐silicon‐interposer interconnects

Jawed

Afridi

Anjum

et al. 2016

Circuit Theory & Apps

View full text Add to dashboard Cite

This paper presents four topologies of voltage-mode un-terminated IO cells in 28-nm CMOS for singleended rail-to-rail signaling over a passive interposer die in 2.5D configuration for >1Gbps data rates. The presented design explores the existing IO design-space from a 2.5D viewpoint, optimizing existing topologies from area, speed, power and protection perspectives, with a higher degree of configurability in the form of pre-emphasis and slew-rate control. The transmitter (TX) embeds pre-emphasis to enhance high-frequency components of the signal for longer low-pass natured channels. The TX also implements slew-rate control to minimize reflections on shorter channels because of impedance discontinuities and also to minimize simultaneous switching noise. Level-shifting capability embedded in the receiver (RX) enables multi-technology interfacing where different dies are signaling at their core voltages (range: 0.7 V-1.8 V) instead of following a particular signaling standard. The measurement results of the transceivers, over a interposer of length of 3.5 mm, demonstrate ±5% duty-cycle distortion with 700 μW at 500 MHz/0.8-V-signaling on the channel with jitter of 20 ps, ±10% duty-cycle distortion with 1.8 mW at 1Gbps/0.9-V signaling with jitter of 20 ps, ±10% duty-cycle distortion with 2 mW at 2Gbps/0.7-V signaling for 1-V receiver core voltage with a jitter of 10 ps. of limiter material or functional errors because of electro-thermal coupling or excessive leakage currents which can form a positive feedback loop with the temperature leading to thermal run-away problem [10,11]. Moreover, the thermal expansion coefficients of TSV material and substrate are different, which can result in large temperature induced mechanical stress again leading to nonuniform distribution of delay across the area [5].Recently, 2.5D IC stacking has emerged as a viable alternative because of its higher mechanical and thermal reliability with a comparable interconnect density [10,12,13]. Several flip-chip dies are attached with fine-pitch micro-bumps to a single passive interposer die also known as throughsilicon-interposer (TSI) communication. This interposer die allows connections between adjacently placed multi-technology dies as well as connections to the package, providing low interconnect delay, high-bandwidth, multi-technology interfacing and reduced ESD protection requirements for die-to-die connections [14]. Moreover, although incurring the cost of adding a passive Si interposer, TSI avoids the issues faced by TSV based 3D configuration related to the high-temperature gradients because of poor thermal distribution, difficult IO planning, large keep-out areas and reliable manufacturing [10,13,15,16]. When compared with traditional backplane through-PCB interconnections which span lengths of few inches (>25 cm), TSI interconnects are much shorter (few mm) in length [2], which is one of the main reasons for their enhanced performance. For example, at 5 Gbps a 25-cm-long PCB track suffers from approximately 20-dB additional channel l...

show abstract

A high speed, low voltage to high voltage level shifter in standard 1.2 V 0.13 μm CMOS

Cited by 18 publications

References 5 publications

Nanosecond Delay Floating High Voltage Level Shifters in a 0.35 $\mu$m HV-CMOS Technology

Nanosecond Delay Floating High Voltage Level Shifters in a 0.35 $\mu$m HV-CMOS Technology

Analysis and implementation of a power management unit with a multiratio switched capacitor DC–DC converter for a supercapacitor power supply

IO circuit design for 2.5D through‐silicon‐interposer interconnects

Contact Info

Product

Resources

About