Nanowire Addressing with Randomized-Contact Decoders

Abstract

Methods for assembling crossbars from nanowires (NWs) have been designed and implemented. Methods for controlling individual NWs within a crossbar have also been proposed, but implementation remains a challenge. A NW decoder is a device that controls many NWs with a much smaller number of lithographically produced mesoscale wires (MWs). Unlike traditional demultiplexers, all proposed NW decoders are assembled stochastically. In a randomized-contact decoder (RCD) [11], for example, field-effect transistors are randomly created at about half of the NW/MW junctions.In this paper, we tightly bound the number of MWs required to produce a correctly functioning RCD with high probability. We show that the number of MWs is logarithmic in the number of NWs, even when errors occur. We also analyze the overhead associated with controlling a stochastically assembled decoder. As we explain, lithographically-produced control circuitry must store information regarding which MWs control which NWs. This requires more area than the MWs themselves, but has received little attention elsewhere.

Stochastic nanoscale addressing for logic

“…Which NWs a given MW controls (makes nonconducting) is determined by the decoder's stochastic assembly process. A range of proposed decoders can be modeled using a binary model with errors [6].…”

“…This allows a bit of data to be written by altering the physical state of the nanowires' point(s) of intersection (see Figure 1). A range of technologies have been presented to realize decoders for memories including using masks [1], [2], axial NW encoding [3], [4], radial NW encoding [5], random particle deposition [6], rotational offsets of intersecting sets of wires [7], [8], and micro-to-nano addressing blocks [9].…”

“…We have analyzed the area occupied by memory decoders and crossbars for a variety of stochastic assembly methods to determine the conditions under which the area is minimized. We have studied encoded NW decoders [10], randomized-contact decoders [6], masked-based decoders [11], and decoders for radially encoded NWs [5]. In all cases tight bounds have been derived on M , the number of MWs required to address N a out of N NWs with high probability.…”

An Outlook on Design Technologies for Future Integrated Systems

“…The architecture of decoders for interfacing to nanoarrays is an important issue [12], [105]. All proposed solutions, either suggested as concepts [32], [56], [109], or implemented on real chips [8], rely on the principle of a linear array of transistors that can be aligned with the nanowires.…”

Analysis of a Mask-Based Nanowire Decoder

“…This still implies that more than 70 MWs are required, which is significantly more than the number required by other decoding technologies when using the same addressing strategy. Under the same conditions less than 30 MWs are necessary when either an encoded-NW or randomizedcontact decoder is used [19], [29].…”