Narrowing the margins with elastic clocks

Abstract

The continuous shrinking of process geometries increases variability and demands for conservative margins that have a negative impact on performance. With conventional clocks, the cycle period has to be defined to accommodate the worst-case variations during the lifetime of the circuit. Elastic Clocks arise as a new paradigm to reduce the margins without sacrificing robustness. Their cycle-by-cycle adaptation to static and dynamic variability enables the use of reduced margins that only need to cover the differential variability of the circuit delays with regard to the elastic period. Given the substantial spatio-temporal correlation within every die, a significant reduction in the margins required to cover process variability, voltage and temperature fluctuations and aging can be achieved.

Variation-aware approaches with power improvement in digital circuits

“…The authors propose a hybrid approach which is a combination of ABB and synthesis. In [31] using the immediate adaptability of elastic clocks with dynamic variations of the circuit, authors have reduced delay variation of critical paths. A lookup table-based ABB approach to reduce variation impacts and leakage power is proposed in [32].…”