NB-IoT and GNSS All-In-One System-On-Chip Integrating RF Transceiver, 23-dBm CMOS Power Amplifier, Power Management Unit, and Clock Management System for Low Cost Solution

Lee, Jongsoo; Han, Jae‐Hoon; Lo, Chi-Lun; Kim, Wan; Kim, Seung-Jin; Kang, Bongsoon; Han, Juyoung; Jung, Sangdon; Nomiyama, Takahiro; Cho, Thomas Byunghak; Kang, I-Seok

doi:10.1109/jssc.2020.3012742

Cited by 29 publications

(12 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Nevertheless, the power consumption figures in Table 3 offer an overall receiver power consumption estimate that fits well within the typical ranges reported in other designs. We also emphasize that these perblock power consumption values are practical values adopted from recently published circuit designs and are used to evaluate the EE performance of our investigated system-level solutions [7], [8], [25], [26].…”

Section: Energy Efficiency and Numerical Resultsmentioning

confidence: 99%

“…The Bussgang coefficient values are tabulated in Table 2 as a function of b. The linear model in (7) introduces a distortion parameter d that is uncorrelated with the received signal y. Therefore, the quantization noise power can be calculated as…”

Section: B Bussgang's Linear Modelmentioning

confidence: 99%

“…For Differential-PSK (DPSK), the model in (7) has to be modified since the current transmitted symbol is modulated differentially with respect to the previous transmitted symbol. By adding the subscript k to represent the time index, and denoting the original (i.e.…”

Section: B Siso Differential Psk Systems With Low-resolution Adcmentioning

confidence: 99%

“…Circuit-level solutions include numerous circuit design ideas proposed in the literature for low-power IoT transceivers such as adding a power management unit for regulating the operation of other system blocks to minimize overall power consumption [7]. In addition, the authors of [8] proposed adding hardware accelerators and a sensor-hub controller in a fully-integrated system-on-a-chip architecture.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Receiver Energy Efficiency and Transmission Latency Analysis of Outage-Constrained Differential PSK With a Finite Resolution ADC

Helwa

Al-Dhahir

2021

IEEE Access

View full text Add to dashboard Cite

We consider a power constrained downlink communication scenario where energy efficiency, reliability, and latency take precedence over rate, as in some Internet of Things (IoT) applications. To reduce its receiver power consumption and complexity, we assume that the IoT device has a single RF chain and investigate the finite-resolution analog-to-digital converter (ADC) operation with differential Phase Shift Keying (PSK) modulation. A lower ADC resolution leads to an exponential decrease in power consumption, while adopting differential PSK enables the use of a low-cost detector with no channel state information (CSI) or carrier phase recovery circuitry. Our main goal in this article is to compare, both analytically and numerically using representative IoT system design parameters, the receiver energy efficiency of the proposed differential PSK system with a coherent PSK system that uses estimated CSI under reliability and latency constraints in Rayleigh slow-fading and ADC quantization distortion conditions. To mitigate the ADC finite-resolution effects without requiring CSI at the receiver or transmitter, we propose and analyze a PSK differentially-modulated Alamouti space-time block transmission scheme with only two RF chains at the transmitter while still restricting the IoT device to have a single RF chain. Our results demonstrate that in the considered low-rate, and outage and latency-constrained scenario with stringent power consumption requirements, differentially-modulated Alamouti transmissions to a single RF-chain IoT device with a lowresolution ADC is an attractive choice in terms of receiver energy efficiency, reliability, and transmission latency.

show abstract

Section: Energy Efficiency and Numerical Resultsmentioning

confidence: 99%

Section: B Bussgang's Linear Modelmentioning

confidence: 99%

Section: B Siso Differential Psk Systems With Low-resolution Adcmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Receiver Energy Efficiency and Transmission Latency Analysis of Outage-Constrained Differential PSK With a Finite Resolution ADC

Helwa

Al-Dhahir

2021

IEEE Access

View full text Add to dashboard Cite

show abstract

“…Despite the mentioned parameters, the area occupation (1.3 mm × 1.4 mm) is larger than the dictated area for our design, which has 1.2 mm × 0.9 mm available area for the design. In [6], a dual-band transmitter is proposed in two transmit paths for low and high bands. A twostage differential and cascade structured cores are used in parallel with each other that are enabled to provide the gain steps.…”

Section: Introductionmentioning

confidence: 99%

A Dual-Band 47-dB Dynamic Range 0.5-dB/Step DPA with Dual-Path Power-Combining Structure for NB-IoT

Rad

Kim

et al. 2022

Sensors

View full text Add to dashboard Cite

This paper presents a digital power amplifier (DPA) with a 43-dB dynamic range and 0.5-dB/step gain steps for a narrow-band Internet of Things (NBIoT) transceiver application. The proposed DPA is implemented in a dual-band architecture for both the low band and high band of the frequency coverage in an NBIoT application. The proposed DPA is implemented in two individual paths, power amplification, and power attenuation, to provide a wide range when both paths are implemented. To perform the fine control over the gain steps, ten fully differential cascode power amplifier cores, in parallel with a binary sizing, are used to amplify power and enable signals and provide fine gain steps. For the attenuation path, ten steps of attenuated signal level are provided which are controlled with ten power cores, similar to the power amplification path in parallel but with a fixed, small size for the cores. The proposed implementation is finalized with output custom-made baluns at the output. The technique of using parallel controlled cores provides a fine power adjustability by using a small area on the die where the NBIoT is fabricated in a 65-nm CMOS technology. Experimental results show a dynamic range of 47 dB with 0.5-dB fine steps are also available.

show abstract

Design and Optimization of a Sub-threshold CMOS LDO Regulator with Improved Performance for IoT and Wearable Devices

Ameziane,

Zared,

Akhmal

et al. 2024

Advances in Science, Technology &Amp; Innovation

View full text Add to dashboard Cite

NB-IoT and GNSS All-In-One System-On-Chip Integrating RF Transceiver, 23-dBm CMOS Power Amplifier, Power Management Unit, and Clock Management System for Low Cost Solution

Cited by 29 publications

References 21 publications

Receiver Energy Efficiency and Transmission Latency Analysis of Outage-Constrained Differential PSK With a Finite Resolution ADC

Receiver Energy Efficiency and Transmission Latency Analysis of Outage-Constrained Differential PSK With a Finite Resolution ADC

A Dual-Band 47-dB Dynamic Range 0.5-dB/Step DPA with Dual-Path Power-Combining Structure for NB-IoT

Design and Optimization of a Sub-threshold CMOS LDO Regulator with Improved Performance for IoT and Wearable Devices

Contact Info

Product

Resources

About