This paper presents a register-transistor level (RTL) based convolutional neural network (CNN) for biosensor applications. Biosensor-based diseases detection by DNA identification using biosensors is currently needed. We proposed a synthesizable RTL-based CNN architecture for this purpose. The adopted technique of parallel computation of multiplication and accumulation (MAC) approach optimizes the hardware overhead by significantly reducing the arithmetic calculation and achieves instant results. While multiplier bank sharing throughout the convolutional operation with fully connected operation significantly reduces the implementation area. The CNN model is trained in MATLAB® on MNIST® handwritten dataset. For validation, the image pixel array from MNIST® handwritten dataset is applied on proposed RTL-based CNN architecture for biosensor applications in ModelSim®. The consistency is checked with multiple test samples and 92% accuracy is achieved. The proposed idea is implemented in 28 nm CMOS technology. It occupies 9.986 mm2 of the total area. The power requirement is 2.93 W from 1.8 V supply. The total time taken is 8.6538 ms.

No abstract

This paper proposes a high-gain low-noise current signal detection system for biosensors. When the biomaterial is attached to the biosensor, the current flowing through the bias voltage is changed so that the biomaterial can be sensed. A resistive feedback transimpedance amplifier (TIA) is used for the biosensor requiring a bias voltage. Current changes in the biosensor can be checked by plotting the current value of the biosensor in real time on the self-made graphical user interface (GUI). Even if the bias voltage changes, the input voltage of the analog to digital converter (ADC) does not change, so it is designed to plot the current of the biosensor accurately and stably. In particular, for multi-biosensors with an array structure, a method of automatically calibrating the current between biosensors by controlling the gate bias voltage of the biosensors is proposed. Input-referred noise is reduced using a high-gain TIA and chopper technique. The proposed circuit achieves 1.8 pArms input-referred noise with a gain of 160 dBΩ and is implemented in a TSMC 130 nm CMOS process. The chip area is 2.3 mm2, and the power consumption of the current sensing system is 12 mW.

This paper presents a digital power amplifier (DPA) with a 43-dB dynamic range and 0.5-dB/step gain steps for a narrow-band Internet of Things (NBIoT) transceiver application. The proposed DPA is implemented in a dual-band architecture for both the low band and high band of the frequency coverage in an NBIoT application. The proposed DPA is implemented in two individual paths, power amplification, and power attenuation, to provide a wide range when both paths are implemented. To perform the fine control over the gain steps, ten fully differential cascode power amplifier cores, in parallel with a binary sizing, are used to amplify power and enable signals and provide fine gain steps. For the attenuation path, ten steps of attenuated signal level are provided which are controlled with ten power cores, similar to the power amplification path in parallel but with a fixed, small size for the cores. The proposed implementation is finalized with output custom-made baluns at the output. The technique of using parallel controlled cores provides a fine power adjustability by using a small area on the die where the NBIoT is fabricated in a 65-nm CMOS technology. Experimental results show a dynamic range of 47 dB with 0.5-dB fine steps are also available.