A Configurable and Fully Synthesizable RTL-Based Convolutional Neural Network for Biosensor Applications

Kumar, Pervesh; Yingge, Huo; Ali, İmran; Pu, Young-Gun; Hwang, Keum Cheol; Yang, Youngoo; Jung, Yeon Jae; Huh, Hyungki; Kim, Chanju; Yoo, Joon-Mo; Lee, Kang-Yoon

doi:10.3390/s22072459

Cited by 3 publications

(2 citation statements)

References 29 publications

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“…In [10], the highest throughput was reached by implementing adaptive switching between shallow and deep networks, and a new CNN architecture was proposed. A novel architecture to implement CNN was proposed in [11]. The proposed CNN architecture was trained on MATLAB for digit recognition for the MNIST dataset.…”

Section: Introductionmentioning

confidence: 99%

Energy-Efficient Precision-Scaled CNN Implementation With Dynamic Partial Reconfiguration

et al. 2022

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A convolutional neural network (CNN) classifies images with high accuracy. However, CNN operation requires a large number of computations which consume a significant amount of power when implemented on hardware. Precision scaling has been recently used to reduce the hardware requirements and power consumption. In this paper, we present an energy-efficient precision-scaled CNN (EEPS-CNN) architecture. Furthermore, the Field Programmable Gate Array (FPGA) is reconfigured during run time using Dynamic Partial Reconfiguration (DPR). If the battery level decreases, the EEPS-CNN design with the most appropriate power consumption is configured on the FPGA. DPR enables recognition applications to run at a low power budget while sacrificing minor accuracy instead of termination. The proposed architecture is implemented on Xilinx XC7Z020 FPGA and is evaluated on three datasets: MNIST, F-MNIST, and SVHN datasets. The results show a 2.2X, 2.39X, and 2.38X reduction in the energy consumption, respectively, while using only 7 bits to represent all inputs and network parameters. The accuracy of the proposed EEPS-CNN is only 0.53%, 3.67%, and 0.88% less than 32-bit floating-point architectures for MNIST, F-MNIST, and SVHN, respectively. Moreover, the results show up to 92.91X and 4.84X reductions in the power and energy consumption of the proposed EEPS-CNN compared to related designs developed for the MNIST dataset.

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Section: Introductionmentioning

confidence: 99%

Energy-Efficient Precision-Scaled CNN Implementation With Dynamic Partial Reconfiguration

et al. 2022

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“…Building high-performance custom hardware is challenging in terms of the design process [21][22][23]. The hardware architecture for such complex algorithms using low-level HDL requires considerable time and effort.…”

Section: Introductionmentioning

confidence: 99%

A Study on the Design Procedure of Re-Configurable Convolutional Neural Network Engine for FPGA-Based Applications

et al. 2022

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Convolutional neural networks (CNNs) have become a primary approach in the field of artificial intelligence (AI), with wide range of applications. The two computational phases for every neural network are; the training phase and the testing phase. Usually, testing is performed on high-processing hardware engines, however, the training part is still a challenge for low-power devices. There are several neural accelerators; such as graphics processing units and field-programmable-gate-arrays (FPGAs). From the design perspective, an efficient hardware engine at the register-transfer level and efficient CNN modeling at the TensorFlow level are mandatory for any type of application. Hence, we propose a comprehensive, and step-by-step design procedure for a re-configurable CNN engine. We used TensorFlow and Keras libraries for modeling in Python, whereas the register-transfer-level part was performed using Verilog. The proposed idea was synthesized, placed, and routed for 180 nm complementary metal-oxide semiconductor technology using synopsis design compiler tools. The proposed design layout occupies an area of 3.16 × 3.16 mm2. A competitive accuracy of approximately 96% was achieved for the Modified National Institute of Standards and Technology (MNIST) and Canadian Institute for Advanced Research (CIFAR-10) datasets.

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Verification of Hardware Resource Utilization through High Level Synthesis for FPGA Implementation

Pandey,

Asati,

Shenoy

et al. 2023

2023 4th IEEE Global Conference for Advancement in Technology (GCAT)

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A Configurable and Fully Synthesizable RTL-Based Convolutional Neural Network for Biosensor Applications

Cited by 3 publications

References 29 publications

Energy-Efficient Precision-Scaled CNN Implementation With Dynamic Partial Reconfiguration

Energy-Efficient Precision-Scaled CNN Implementation With Dynamic Partial Reconfiguration

A Study on the Design Procedure of Re-Configurable Convolutional Neural Network Engine for FPGA-Based Applications

Verification of Hardware Resource Utilization through High Level Synthesis for FPGA Implementation

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