Nb multilayer planarization technology for a subnanosecond Josephson 1K-bit RAM

Full-Gate Verification of Superconducting Integrated Circuit Layouts With InductEx

“…In the AIST STP 2.5-kA/cm 2 [18], [19] and ADP2 10-kA/cm 2 processes [20], [21], the resistive layer RES1 is sandwiched inside isolation layer GC, which also separates the first metal layer/base electrode (BAS, or the M1 layer) from ground (GP, or the M0 layer). In layout, a via on layer GC connects BAS to GP, whereas a contact hole specified on layer RC connects BAS to RES1 through a part of the GC isolation.…”

“…(b) Hypres 4.5-kA/cm 2 process. (c) AIST ADP2 process (for AIST STP; the thickness of layer RES is 0.08 μm [19], and σ = 10.417 S/μm). Some layer parameters are omitted for brevity.…”

Superconductivity and its Application

“…[14][15] J Theoretical study shows[16] that Phase Quanntum Tunneling (PQT) can exist in small superconductor junction which is dual to Josephson tunneling. Two macroscopic quantum effects are expected to occur in the region shown inFig.l.11-2.Junction and Device FabricationMost groups with experience in thin film junction fabrication are attempting to produce all-refactory structures based on Nb, Ti, and NbN [4][17]. Fairly reliable RF plasma and ion beam oxidation procedures for Nb have been developed, and there is much work on non-native barriers, such as A1203,MgO and …”

Mechanism for the Local Planarization of Microscopically Rough Surfaces by Drying Thin Films of Spin‐Coated Polymer/Solvent Solutions

“…The yield and reliability of the devices produced often depend on the degree of smoothness of the polymer film. Finally, polymer films are becoming increasingly important as sac-rificial layers for etch-back processes (14)(15)(16)(17)(18)(19)(20)(21) in which polymer is spin coated on some topographically rough substrate that may be an insulator such as phosphosilicate glass or a conductor such as tungsten. The effect of the polymer coating is again to smooth the substrate.…”