NBT stress-induced degradation and lifetime estimation in p-channel power VDMOSFETs

Effects of pulsed negative bias temperature stressing in p-channel power VDMOSFETs

“…NBTI can put serious limit to a device lifetime, so one of the main goals of our NBTI studies was to estimate the normal operation lifetime of investigated p-channel power VDMOSFETs by using the experimental data obtained under the accelerated NBT stress conditions. Considering the above differences in the observed effects between the static and pulsed NBT stressing, the predictions based on the results of static NBT stressing [15], [16] may underestimate the lifetime, so the proper approach is to assess the lifetime under the pulsed NBT stress conditions, which are closer to those met by devices in real applications. Our experimental devices were the power transistors, so we could assume maximum normal bias and temperature to be, for example V G = -20 V and T = 100 o C. Either of several device electrical parameters, such as threshold voltage, transconductance, or drain current, can be used as degradation monitor for the lifetime estimation [30], [31].…”

“…Earlier investigations have shown that the pulsed (also referred to as AC) NBT stress creates less significant degradation than the static (DC) stress owing to a dynamic recovery effect (a part of degradation created by the preceding stress voltage pulse is neutralized and/or annealed during the fraction of period corresponding to the "low" level of the pulsed stress voltage and has to be restored upon arrival of the next voltage pulse) [10]- [14]. Accordingly, the lifetime predictions based on static NBT stress [15], [16], where the transistor was continuously kept "on", might be wrong, and it is thus important to estimate device lifetime under the pulsed NBT stress conditions. This paper provides a review of our recent research of the effects of pulsed bias NBT stressing in p-channel power VDMOSFETs [17]- [20].…”

NBT stress and radiation related degradation and underlying mechanisms in power VDMOSFETs

“…NBT stress-induced threshold voltage instabilities in commercial power VDMOSFETs, as well as the implications of related degradation on device lifetime have been extensively investigated in our research in the last decade [27,[42][43][44]. Although in many experiments devices have been subjected to various NBT stress (static or pulsed) and annealing conditions [9,23,25,45,46,[48][49][50][51][52], in this section a part of results obtained during static NBT stress and annealing is presented, with attention to insight into the NBTI as a result of sequential NBT stress and bias annealing steps.…”

Negative bias temperature instabilities in sequentially stressed and annealed p-channel power VDMOSFETs

“…Degradation of power MOSFETs under various stresses (irradiation, high field, temperature, and hot carrier injection) has been subject of extensive research [5,6], but only few authors seem to have addressed the NBTI in these devices [7][8][9][10]. Increased gate oxide fields and elevated temperatures are typically found in burn-in tests [11], but can be approached during routine operation of power MOSFET in automotive and industrial applications as well [8].…”

“…Our earlier papers were dealing with mechanisms of degradation and lifetime estimation in p-channel power VDMOSFETs subjected to continuous NBT stress [9,10]. This paper, revealing the behaviour of threshold voltage and analysing the underlying changes of gate oxide-trapped charge and interface trap densities in the same devices subjected to a sequence of NBT stress and bias annealing steps, is intended to provide better insight into the NBTI related phenomena.…”