NBTI Degradation: A Problem or a Scare?

Saluja, Kewal K.; Vijayakumar, S.; Sootkaneung, Warin; Yang, Xaingning

doi:10.1109/vlsi.2008.43

Cited by 24 publications

(13 citation statements)

References 18 publications

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“…During recovery phase, the interface traps are annealed by hydrogen species and thus, the degradation of the threshold voltage V th is partially recovered. According to a comprehensive device-level predictive model covering both static and dynamic NBTI degradation [17,21], the stress phase can be expressed as…”

Section: Nbtimentioning

confidence: 99%

An online wear state monitoring methodology for off-the-shelf embedded processors

Arunachalam

Chantem

Dick

et al. 2015

2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

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The continued scaling of transistors has led to an exponential increase in on-chip power density, which has resulted in increasing temperature. In turn, the increase in temperature directly leads to the increase in the rate of wear of a processor. Negative-bias temperature instability (NBTI) is one of the most dominant integrated circuit (IC) failure mechanisms [5,13] that strongly depends on temperature. NBTI manifests in the form of increased circuit delays which can lead to timing failures and processor crashes. The ability to monitor the wear progression of a processor due to NBTI is valuable when designing real-time embedded systems. While NBTI can be detected using wear state sensors, not all chips are equipped with these sensors because detecting wear due to NBTI requires modifications to the chip design and incurs area and power overhead. NBTI sensor data may also not be exposed to users in software. In addition, wear sensors cannot take into account variations in wear due to the differences in the wear sensor devices and the other functional devices and their operating conditions. In this thesis, I propose a lightweight, online methodology to monitor the wear process due to NBTI for off-the-shelf embedded processors. Our proposed method requires neither data on the threshold voltage and critical paths nor additional hardware.Our methodology can also be extended to predict the wear progression due to some other dominant IC failure mechanisms. Experiments on embedded processors provide insights on iv NBTI wear progression over time. This knowledge can be used to design real-time embedded systems that explicitly consider runtime wear progression to increase predictability and maintain lifetime reliability requirements. In turn, the increase in temperature directly leads to the increase in the rate of wear of a processor. Negative-bias temperature instability (NBTI) is one of the most dominant integrated circuit (IC) failure mechanisms [5,13] that strongly depends on temperature.NBTI manifests in the form of increased circuit delays which can lead to the processor not meeting its timing constraints and result in processor crashes. The ability to monitor the wear progression of a processor due to NBTI is valuable when designing real-time embedded systems. Real-time embedded systems are systems whose tasks are performed correctly and in a timely manner and predictable manner. While NBTI can be detected using wear state sensors, not all chips are equipped with these sensors because detecting wear due to NBTI requires modifications to the chip design and incurs area and power overhead. NBTI sensor data may also not be exposed to users in software. In addition, wear sensors cannot take into account variations in wear due to the differences in the wear sensor devices and the other functional devices and their operating conditions. In this thesis, we propose a vi lightweight, online methodology to monitor the wear process due to NBTI for off-the-shelf embedded processors. Our proposed method requires neither diffi...

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Section: Nbtimentioning

confidence: 99%

An online wear state monitoring methodology for off-the-shelf embedded processors

Arunachalam

Chantem

Dick

et al. 2015

2015 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

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“…The BTI-Refresh technique can be implemented at a gatelevel as a design-for-reliability methodology [12]. The following explains the overall design methodology.…”

Section: Design For Reliability Methodologymentioning

confidence: 99%

“…The design for reliability (DFR) methodologies proposed in literature thus far for logic paths relies on guard banding the paths to mitigate the degradation effects [9][10][11][12][13]. Hence, the fundamental requirement is an accurate estimation of degradation such that an exact design margin can be applied.…”

Section: Related Workmentioning

confidence: 99%

“…However, it requires an accurate prediction of α for each and every transistor at a circuit/system level. Many research teams have contributed to different ways of estimating α [6] [9][10][11][12][13]. The authors in [6] have shown the impact of levels of abstraction i.e., circuit level, gate level or transistor level, on the signal probability estimation.…”

Section: Introductionmentioning

confidence: 99%

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Performance entitlement by exploiting transistor's BTI recovery

Arasu

Nourani

Reddy

et al. 2013

International Symposium on Quality Electronic Design (ISQED)

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The inherent problem in signal probability (α) prediction has limited the scope of exploiting the transistor's BTI recovery at circuit level. In this paper, we present a design-forreliability (DFR) methodology for digital designs, BTI_Refresh, that instead of relying on predicting α, sets it to a known value (~0.5) such that the BTI stress effects are alleviated and a predicted recovery effect could be guaranteed at circuit level. The technique can be applied equally to both NBTI and PBTI. Experimental results using Cadence Relxpert on critical paths extracted from industry designs show that with a negligible power, area overhead, a significant improvement (50%) in the total degradation of critical path performance with respect to end-of-life models is achievable.

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“…NBTI is mainly caused by the interfacial layer hydrogen diffusion into the SiO 2 insulator and partial recovery associated with reduction in traps [20]. NBTI manifests as an increase in the threshold voltage magnitude and a decrease in drain current.…”

Section: Key Parameters and Reliability Issuesmentioning

confidence: 99%

Process and temperature robust voltage multiplier design for RF energy harvesting

Yuan

2015

Microelectronics Reliability

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NBTI Degradation: A Problem or a Scare?

Cited by 24 publications

References 18 publications

An online wear state monitoring methodology for off-the-shelf embedded processors

An online wear state monitoring methodology for off-the-shelf embedded processors

Performance entitlement by exploiting transistor's BTI recovery

Process and temperature robust voltage multiplier design for RF energy harvesting

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