Near-ideal subthreshold swing MoS₂ back-gate transistors with an optimized ultrathin HfO₂ dielectric layer

Abstract

In this paper, a near-ideal subthreshold swing MoS 2 back-gate transistor with an optimized ultrathin HfO 2 dielectric layer is reported with detailed physical and electrical characteristics analyses. Ultrathin (10 nm) HfO 2 films created by atomic-layer deposition (ALD) at a low temperature with rapid-thermal annealing (RTA) at different temperatures from 200 °C to 800 °C have a great effect on the electrical characteristics, such as the subthreshold swing (SS), on-to-off current (I ON /I OFF ) ratio, etc, of the MoS 2 devices. Physical examinations are performed, including x-ray diffraction, atomic force microscopy, and electrical experiments of metal-oxidesemiconductor capacitance-voltage. The results demonstrate a strong correlation between the HfO 2 dielectric RTA temperature and the film characteristics, such as film density, crystallization degree, grain size and surface states, inducing a variation in the electrical parameters, such as the leakage, D it , equivalent oxide thickness, SS, and I ON , as well as I ON /I OFF of the MoS 2 field effect transistors with the same channel materials and fabrication methods. With a balance between the crystallization degree and the surface state, the ultrathin (10 nm) HfO 2 gate dielectric RTA at 500 °C is demonstrated to have the best performance with a field effect mobility of 40 cm 2 V −1 s −1 and the lowest SS of 77.6 mV −1 decade, which are superior to those of the control samples at other temperatures. The excellent transistor results with an optimized industry-based HfO 2 ALD and RTA process provide a promising approach for MoS 2 applications into the scaling of the nanoscale CMOS process.

Engineering Field Effect Transistors with 2D Semiconducting Channels: Status and Prospects

“…Charge exchange between oxide defects and trap states in the channel leads to the ubiquitous hysteresis and long‐term drifts of the gate transfer characteristics — often referred in Si technologies as bias‐temperature instabilities (BTI) . Recently, an attempt to improve the quality of comparably thin (10 nm) HfO 2 films has been undertaken by crystallizing them using rapid thermal annealing (RTA), but this methodology appears to be unsuitable to improve the performance of the devices due to the limited thermal stability of most TMDs.…”

“…However, we note that all the literature reports discussed above have studied short channel effects on experimental 2D‐FET technologies that have not been fully optimized. For instance, further development of recently reported devices using 2 nm CaF 2 and even 10 nm HfO 2 might allow further minimization short channel effects for channel lengths in the several nanometer regime.…”

Insulators for 2D nanoelectronics: the gap to bridge

“…To passivate these imperfections, insulators and interfaces have been subjected to various annealing steps to reduce their defectivity, e.g. by the use of rapid thermal annealing (RTA) 38 . However, the resulting density of dangling bonds is still too high and deteriorates the device performance.…”

“…Up to now, a variety of insulators have been already investigated for 2D FETs. The most widely used are thermally grown SiO 2 13,20,58 as a substrate/back-gate, and conventional high-k oxides such as Al 2 O 3 16 and HfO 2 10,38 for top-gated structures. In addition, the 2D crystalline insulator hBN 11,45,58 , as well as the crystalline CaF 2 46 have been used.…”

“…4b we compare D it values from literature 14 , 0.9 nm EOT CaF 2 46 , 1.3 nm EOT PTCDA/HfO 2 40 and exfoliated devices of the latter technology 40 . b Comparison of D it values measured for Si devices 78 and different 2D technologies 38,40,41,43,46,54,[73][74][75][76][77] . c Comparison of SS values for different 2D devices 16,38,40,41,43,46,54,66 with EOT below 10 nm.…”