Near void free hybrid no-flow underfill flip chip process technology

Void Formation Study of Flip Chip in Package Using No-Flow Underfill

“…The underfill flow-induced voiding pattern (as an example shown in Fig. 6) which formed among solders is not desirable for long-term reliability [20]. That is, the void percentages between high and low parameter levels in all three cases were not sufficient to account for the process induced voids.…”

“…The placement force is defined as the applied force on a chip during the placement process, and placement dwell time is defined as the time the placed chip is held during a chip placement process. Since the chip placement speed, among the placement control parameters, was reported as an insignificant factor affecting underfill voids [20], the placement speed was not included in the design matrix for the void formation study 1.…”

“…They investigated the effect of pad geometry on the underfill void formation and found the underfill flow characteristics had a major effect. Colella et al identified some significant factors influencing void formation in no-flow underfills including process design parameters such as underfill dispense pattern, placement parameters, and pad design [20].…”

Development of No-flow Underfill Materials and Processes for Pb-free Flip Chip Applications

“…The extent of outgassing contributed by the substrate can be minimized by subjecting the substrate to appropriate pre-bake conditions. Effect of Dispense Pattern on Voiding: It has been reported by Baldwin et al [10], that the dispense pattern is one of the most significant factors affecting void formation in no-flow underfill materials. Due to the irregular features of the board, and the contact wetting angle of the underfill to the solder mask on the substrate, capture or placement voids (c) Figure 9.…”

“…The presence of these voids immediately after placement will almost certainly result in a voided underfill interface after reflow/cure. By using a hybrid no-flow underfill process [10], the line dispense eliminates the placement/capture voids by virtue of the capillary forces that cause the die to fill the entire gap between the chip and substrate. This dispense pattern also avoids the long flow times associated with the conventional capillary underfill materials, since the no-flow underfill material fills the standoff and forms uniform fillets around the die perimeter during reflow.…”