Necessary nonzero lithography overlay correctables for improved device performance for 110nm generation and lower geometries

Jekauc, Igor; Roberts, Bill; Young, Paul Thomas; Jowett, P.; Ferguson, Reuben; Louks, Sean

doi:10.1117/12.535258

Cited by 1 publication

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“…[15][16][17][18][19] Wafer-induced shift (WIS) is introduced to account for the errors due to pattern asymmetry of the overlay targets. 20 It is induced by process steps such as etch 21 or chemicalmechanical polishing (CMP). [22][23][24] Asymmetric etch causes shift of where the pattern centerline is at its top versus its bottom and the target asymmetry, leading to error of conventional OL metrology.…”

Section: Introductionmentioning

confidence: 99%

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Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

Ito

Hasumi

2019

J. Micro/Nanolith. MEMS MOEMS

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Overlay control has been one of the most critical issues for manufacturing of leading edge semiconductor devices. Introduction of the double patterning process requires stringent overlay control. Conventional optical overlay (Opt-OL) metrology has technical challenges with measurement robustness, solving overlay discrepancy between overlay mark and device pattern, and measuring smaller marks laid out in large numbers within the die accurately for high-order correction. In contrast, scanning electron microscope-based overlay (SEM-OL) metrology can directly measure both overlay targets and actual devices or device-like structures on processed wafers with high spatial resolution. It can be used for reference metrology and optimization of Opt-OL measurement conditions. SEM-OL uses small structures, including actual device patterns, which allows insertion of many SEM-OL targets across a die. Precise overlay distribution can be measured using dedicated SEM-OL mark, improving measurement accuracy and repeatability. To extend SEM-OL capability, we have been developing SEM-OL techniques that can measure not only surface patterns by critical dimension SEM but also buried patterns for leading edge device processes. There are two techniques to detect buried patterns. One is to use high-acceleration voltage SEM, which detects backscattering electron emphasizing material contrast. It has been adopted for overlay measurements for memory and logic devices at after-etch inspection or even after-develop inspection. The other is to utilize charging effect, which reflects voltage contrast at the surface depending on the material properties of underneath structure. SEM-OL measurement using transient voltage contrast has been developed and its capability of overlay measurement has been proven. An overlay measurement algorithm using template matching method has been developed and was applied to dynamic random access memory (DRAM) process monitor in manufacturing. In order to extend SEM-OL metrology to beyond 3-nm node logic and cutting-edge DRAM devices (half pitch = 14 nm), we are improving measurement precision of detecting buried patterns and measurement throughput by developing optimized SEM-OL mark.

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Section: Introductionmentioning

confidence: 99%

“…Nonzero overlay correction in lithography, taking into account pre-and postprocessing, was evaluated to improve final pattern and yield. 21 SEM such as critical dimension SEM (CD-SEM) is generally used for measurement of CD in semiconductor production. SEM-OL metrology had been discussed for decades.…”

Section: Introductionmentioning

confidence: 99%

Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

Ito

Hasumi

2019

J. Micro/Nanolith. MEMS MOEMS

View full text Add to dashboard Cite

show abstract

Necessary nonzero lithography overlay correctables for improved device performance for 110nm generation and lower geometries

Cited by 1 publication

References 0 publications

Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

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