As semiconductor manufacturing has entered into the nanoscale era, Negative Bias Temperature Instability (NBTI) has become one of the most significant aging mechanisms leading to reliability issues. This paper presents ReverseAge, a technique that detects delay due to NBTI and utilizes design timing margins to ensure reliable circuit operation. First, it presents a scheme to detect the NBTI induced delay. Second, it presents a technique to tolerate the errors; the technique exploits the available design timing margins to compensate for the NBTI induced delay. The evaluation of ReverseAge has been performed by integrating it in an ISCAS-89 benchmark circuit. The simulation results show 3× reliability improvements with respect to state-of-the-art. The improvement comes at the cost of 3.77% area and 1.4% power overheads.