Negative Capacitance of Silicon Diode with Deep Level Traps

Noguchi, Takashi; Kitagawa, M.; Taniguchi, I.

doi:10.1143/jjap.19.1423

Cited by 28 publications

(16 citation statements)

References 1 publication

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“…Similar results of the NC behavior have been reported in the literature [27][28][29][30][31][32]. Several suggestions have been proposed for the exact origin of NC [24][25][26][27][28][29][30][31]35]. Among them Jones et al [24] stated that relaxation-like material is responsible for NC because of the injection of holes which recombine easily with the free electron charge of the dipole at M/S interface, also another origin of NC may be high resistivity materials, and it has been clearly shown by them [24].…”

Section: Resultssupporting

confidence: 78%

Temperature dependent negative capacitance behavior of Al/rhodamine-101/n-GaAs Schottky barrier diodes and Rs effects on the C–V and G/ω–V characteristics

Vural

Şafak

Türüt

et al. 2012

Journal of Alloys and Compounds

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Section: Resultssupporting

confidence: 78%

Temperature dependent negative capacitance behavior of Al/rhodamine-101/n-GaAs Schottky barrier diodes and Rs effects on the C–V and G/ω–V characteristics

Vural

Şafak

Türüt

et al. 2012

Journal of Alloys and Compounds

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“…In most cases, the phenomenon has been observed in the presence of traps for a wide range of materials such as silicon [20], [21], III-V semiconductors [13], [16], [18], [22], [23] and organic semiconductors [14], [15], [24]. Since Salahuddin [7] proposed the application of NC for steep SS FETs, ferroelectric materials have been subject of a number of reports showing their NC properties [25]- [27].…”

Section: Introductionmentioning

confidence: 99%

Charge Trapping Mechanism Leading to Sub-60-mV/decade-Swing FETs

Daus

Vogt

Münzenrieder

et al. 2017

IEEE Trans. Electron Devices

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(2017) Charge trapping mechanism leading to sub-60-mV/decade-Swing FETs. IEEE Transactions on Electron Devices, 64 (7). pp. 2789 -2796 This version is available from Sussex Research Online: http://sro.sussex.ac.uk/68771/ This document is made available in accordance with publisher policies and may differ from the published version or from the version of record. If you wish to cite this item you are advised to consult the publisher's version. Please see the URL above for details on accessing the published version. Copyright and reuse:Sussex Research Online is a digital repository of the research output of the University.Copyright and all moral rights to the version of the paper presented here belong to the individual author(s) and/or other copyright owners. To the extent reasonable and practicable, the material made available in SRO has been checked for eligibility before being made available.Copies of full text items generally can be reproduced, displayed or performed and given to third parties in any format or medium for personal research or study, educational, or not-for-profit purposes without prior permission or charge, provided that the authors, title and full bibliographic details are credited, a hyperlink and/or URL is given for the original metadata page and the content is not changed in any way. Abstract-In this work, we present a novel method to reduce the subthreshold swing of field-effect transistors below 60 mV/dec. Through modeling, we directly relate trap charge movement between the gate electrode and the gate dielectric to subthreshold swing reduction. We experimentally investigate the impact of charge exchange between a Cu gate electrode and a 5 nm thick amorphous Al2O3 gate dielectric in an InGaZnO4 thin-film transistor. Positive trap charges are generated inside the gate dielectric while the semiconductor is in accumulation. During the subsequent de-trapping, the subthreshold swing diminishes to a minimum value of 46 mV/dec at room temperature. Furthermore, we relate the charge trapping/de-trapping effects to a negative capacitance behavior of the Cu/Al2O3 metal-insulator structure. IEEE TRANSACTIONS ON ELECTRON DEVICES

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“…In recent years, some investigations have reported a negative capacitance (NC) [20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37] in the forward bias C-V characteristics. These devices include p-n junctions [31], metal-semiconductor (MS) contacts/Schottky barrier diodes (SBDs) [20,22,27,30], metal-insulator-semiconductor (MIS) structures [24], quantum well infrared photodetectors (QWIPs) [29], UH photodetectors [21], far-infrared detectors [26,34], some dielectric and ferroelectric materials [35,36], and light emitting diodes (LEDs) [23,37].…”

Section: Introductionmentioning

confidence: 99%

“…These devices include p-n junctions [31], metal-semiconductor (MS) contacts/Schottky barrier diodes (SBDs) [20,22,27,30], metal-insulator-semiconductor (MIS) structures [24], quantum well infrared photodetectors (QWIPs) [29], UH photodetectors [21], far-infrared detectors [26,34], some dielectric and ferroelectric materials [35,36], and light emitting diodes (LEDs) [23,37]. The observation of negative capacitance is important because they imply that an increment of bias voltage produces a decrease in the charge on the electrodes [25].…”

Section: Introductionmentioning

confidence: 99%

Temperature dependent negative capacitance behavior in (Ni/Au)/AlGaN/AlN/GaN heterostructures

Arslan

Şafak

Altındal

et al. 2010

Journal of Non-Crystalline Solids

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a b s t r a c tThe temperature dependent capacitance-voltage (C-V) and conductance-voltage (G/x-V) characteristics of (Ni/Au)/Al 0.22 Ga 0.78 N/AlN/GaN heterostructures were investigated by considering the series resistance (R s ) effect in the temperature range of 80-390 K. The experimental results show that the values of C and G/x are strongly functioning of temperature and bias voltage. The values of C cross at a certain forward bias voltage point ($2.8 V) and then change to negative values for each temperature, which is known as negative capacitance (NC) behavior. In order to explain the NC behavior, we drawn the C vs I and G/x vs I plots for various temperatures at the same bias voltage. The negativity of the C decreases with increasing temperature at the forward bias voltage, and this decrement in the NC corresponds to the increment of the conductance. When the temperature was increased, the value of C decreased and the intersection point shifted towards the zero bias direction. This behavior of the C and G/x values can be attributed to an increase in the polarization and the introduction of more carriers in the structure. R s values increase with increasing temperature. Such temperature dependence is in obvious disagreement with the negative temperature coefficient of R or G reported in the literature. The intersection behavior of C-V curves and the increase in R s with temperature can be explained by the lack of free charge carriers, especially at low temperatures.

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Negative Capacitance of Silicon Diode with Deep Level Traps

Cited by 28 publications

References 1 publication

Temperature dependent negative capacitance behavior of Al/rhodamine-101/n-GaAs Schottky barrier diodes and Rs effects on the C–V and G/ω–V characteristics

Temperature dependent negative capacitance behavior of Al/rhodamine-101/n-GaAs Schottky barrier diodes and Rs effects on the C–V and G/ω–V characteristics

Charge Trapping Mechanism Leading to Sub-60-mV/decade-Swing FETs

Temperature dependent negative capacitance behavior in (Ni/Au)/AlGaN/AlN/GaN heterostructures

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