Negative ESD robustness of a novel anti-ESD TGFPTD SOI LDMOS

Zhang, Haipeng; Zhang, Liang; Wang, Dejun; Liu, Guohua; Lin, Mi; Niu, Xiaoyan; Fan, Shenggen

doi:10.1109/apccas.2010.5775049

Cited by 2 publications

(1 citation statement)

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“…Moreover, it is suggested that the parasitic latch-up effect of SOI LIGBT be utilized to improve some of its main electric performances by combining with the BPL SOI substrate [27,28], the integrated anti-ESD structure [29,30], and the structure of thyristor so as to break through the ceilings of both on-state current and forward block voltage based on the proposed VG RF SOI NLIGBT structure.…”

Section: Resultsmentioning

confidence: 99%

Vertical Gate RF SOI LIGBT for SPICs with Significantly Improved Latch-Up Immunity

Zhang

et al. 2011

VLSI Design

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Based on the previous achievements in improving latch-up immunity of SOI LIGBT, process simulation on our proposed VG RF SOI NLIGBT was carried out with TCAD to provide a virtually fabricated device structure. Then, an approximate latching current model was derived according to the condition of minimum regenerative feedback couple between the parasitic dualtransistors. The model indicates that its latching current is a few orders higher than those before. Further verification through device simulation was done with TCAD, which proved that its weak snapback voltage in the off state is about 0.5-2.75 times higher than those breakdown voltages reported before, its breakdown voltage in the off state is about 19 V higher than its weak snapback voltage, and its latching current density in the on state is about 2-3 orders of magnitude higher than those reported before at room temperature due to hole current bypass through P + contact in P-well region. Therefore, it is characterized by significantly improved latch-up immunity.

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Section: Resultsmentioning

confidence: 99%