Negative Gate Transconductance in Gate/Source Overlapped Heterojunction Tunnel FET and Application to Single Transistor Phase Encoder

Trivedi, Amit Ranjan; Ahmed, Kashif; Mukhopadhyay, Saibal

doi:10.1109/led.2015.2388533

Cited by 18 publications

(14 citation statements)

References 8 publications

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“…Its current is based on the tunneling effect at the source to channel edge. Therefore, TFETs can overcome the supply voltage scaling issues, the 60 mV/decade subthreshold slope and power consumption limits of MOSFET devices at room temperature 16,17 . Due to the insignificant band-toband tunneling phenomenon in silicon TFETs, they have low on-currents that one of the major concerns in the design and fabrication of these transistors is to improve their on-current performance.…”

Section: Introductionmentioning

confidence: 99%

“…On the other hand, an increase in on-current causes the RF performances of the TFETs to be enhanced. To enhance the TFET on-currents, many efforts have been made including hetero-structures 11,16,17 , bandgap engineering 18,20 , high mobility and low band-gap materials 20,23 , high-k dielectric materials 24,25 , heterogate-dielectric (HG) 26,27 , dual material gate 28,30 and vertical direction tunneling 31,32 .…”

Section: Introductionmentioning

confidence: 99%

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Enhanced Characteristics of Square-Shaped Extended Source TFET Via Silicon Carbide Polytype (3C-SiC) and a Dopant Pocket Layer

Marjani¹,

Khosroabadi²,

Hosseini³

2017

Orient. J. Chem

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In this paper, for the first time, the square-shaped extended source tunneling field-effect transistor (SES TFET) by means of the silicon carbide polytype (3C-SiC) and dopant pocket layer has been presented. By inserting the silicon carbide polytype as substrate and n-type pocket in the channel at the source edge, on-current is increased by about 10 times compared with the conventional SES TFET because of the reduced losses and energy band modification imposed by the silicon carbide and pocket doping, respectively. Additionally, using calibrated simulations, the SES TFET with 3C-SiC substrate and dopant pocket layer is evaluated in terms of various radiofrequency (RF) parameters, including the gate to source capacitance, gate to drain capacitance, trans conductance, channel resistance, transport time delay, cutoff and maximum oscillation frequencies. The simulation results of the SES TFET with the 3C-SiC substrate and dopant pocket layer exhibits a superior switching-state current ratio ( ̴ ̴ 10 13 ) and a small transport time delay (about 0.15 psec) that is a hopeful candidate for conventional SES TFET.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Enhanced Characteristics of Square-Shaped Extended Source TFET Via Silicon Carbide Polytype (3C-SiC) and a Dopant Pocket Layer

Marjani¹,

Khosroabadi²,

Hosseini³

2017

Orient. J. Chem

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“…However, planar silicon-based TFETs have very low on-state currents (I on ) compared to conventional MOSFETs (typically three to five decades) because of poor band-to-band tunneling efficiency, which is a serious drawback in circuit applications. In order to improve the TFET on-state currents, several techniques have been adopted including heterostructures [4,8], band-gap engineering [9,10], low band gap and high mobility materials [11], gate engineering [12,13], vertical direction tunneling [14], extended source [15][16][17], and source-pocket doping (p-np-n) [18,19].…”

Section: Introductionmentioning

confidence: 99%

A 3D analytical modeling of tri-gate tunneling field-effect transistors

2016

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In this paper, a three-dimensional (3D) analytical solution of the electrostatic potential is derived for the trigate tunneling field-effect transistors (TG TFETs) based on the perimeter-weighted-sum approach. The model is derived by separating the device into a symmetric and an asymmetric double-gate (DG) TFETs and then solving the 2D Poisson's equation for these structures. The subthreshold tunneling current expression is extracted by numerical integrating the band-to-band tunneling generation rate over the volume of the device. It is shown that the potential distributions, the electric field profile, and the tunneling current predicted by the analytical model are in close agreement with the 3D device simulation results without the need of fitting parameters. Additionally, the dependence of the tunneling current on the device parameters in terms of the gate oxide thickness, gate dielectric constant, channel length, and applied drain bias is investigated and also demonstrated its agreement with the device simulations.

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“…N EGATIVE transconductance (NT) devices can be used for ultrahigh frequency filters [1], multilevel logics [2], and phase encoder [3] applications. A variety of transistors have been discovered with NT behavior, like resonant-tunneling transistors [4], [5], modulation-doped FETs [6], [7], MOSFETs [8], [9], and tunneling FETs [3], [10].…”

Section: Introductionmentioning

confidence: 99%

“…A variety of transistors have been discovered with NT behavior, like resonant-tunneling transistors [4], [5], modulation-doped FETs [6], [7], MOSFETs [8], [9], and tunneling FETs [3], [10]. However, most of their peak-to-valley current ratios (PVCR) are less than 10, which are not high enough for the applications.…”

Section: Introductionmentioning

confidence: 99%

Remote Gate-Controlled Negative Transconductance in Gated MIS Tunnel Diode

Liao

Hwu

2016

IEEE Trans. Electron Devices

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The transfer characteristics of a metal-insulatorsemiconductor (MIS) tunnel diode (TD) controlled by a separated MIS TD as gate were investigated. Negative transconductance (NT) exists around the flat-band region in the transfer curve even though the separation between the gate and the MIS TD is large (up to several tens of micrometers). We called it remote gate-controlled NT (RG-NT). With the aid of the Technology Computer Aided Design simulation, the turn around behaviors of the lateral electric field and electron concentration around the flat-band region explain well the RG-NT phenomenon. The peak-to-valley current ratio (PVCR) of the RG-NT increases with the tunnel oxide thickness. The maximum PVCR obtained in this work is 1.3 × 10 6 while the oxide thickness is 3.3 nm.Index Terms-Metal-insulator-semiconductor (MIS) tunnel diode (TD), negative transconductance (NT), peak-to-valley current ratio (PVCR), remote gate-controlled, Schottky barrier modulation.

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Negative Gate Transconductance in Gate/Source Overlapped Heterojunction Tunnel FET and Application to Single Transistor Phase Encoder

Cited by 18 publications

References 8 publications

Enhanced Characteristics of Square-Shaped Extended Source TFET Via Silicon Carbide Polytype (3C-SiC) and a Dopant Pocket Layer

Enhanced Characteristics of Square-Shaped Extended Source TFET Via Silicon Carbide Polytype (3C-SiC) and a Dopant Pocket Layer

A 3D analytical modeling of tri-gate tunneling field-effect transistors

Remote Gate-Controlled Negative Transconductance in Gated MIS Tunnel Diode

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