Negative Offset Operation of Four-Transistor CMOS Image Pixels for Increased Well Capacity and Suppressed Dark Current

Abstract

Abstract-This letter presents an electrical method to reduce dark current as well as increase well capacity of four-transistor pixels in a CMOS image sensor, utilizing a small negative offset voltage to the gate of the transfer (TX) transistor particularly only when the TX transistor is off. As a result, using a commercial pixel in a 0.18 µm CMOS process, the voltage drop due to dark current of the pinned photodiode (PPD) is reduced by 6.1 dB and the well capacity is enhanced by 4.4 dB, which is attributed to the accumulated holes and the increased potential barrier near the PPD, respectively.Index Terms-CMOS image sensor (CIS), dark current, fourtransistor pixel, hole accumulation diode, imager, pinned photodiode (PPD), well capacity.

Extraction and Estimation of Pinned Photodiode Capacitance in CMOS Image Sensors

“…It is the first saturation level FWC1, not the second saturation level FWC2, that determines the maximal charge handling capability of a color sensor. It should be noted that the existence of 2 different saturation levels were not reported in previous studies using monochrome sensors [3], [4], [5], [7]. The first saturation level FWC1 in Fig.…”

“…The V ACC is assumed to be the boundary voltage between the accumulation mode and the depletion mode of the TG. When V TGL is less than the threshold voltage V T but higher than V ACC , TG is depleted or weakly inverted; the subthreshold current is approximately an exponential function of V TGL as in (3). When V TGL is lower than V ACC , TG is biased into the accumulation mode, further decreasing V TGL would not change the TG channel potential anymore; it only increases the voltage difference across the TG gate oxide.…”

“…Each photodiode is isolated from FD by a lateral overflow barrier under the control of the transfer gate (TG). In order to suppress dark leakage, the transfer-gate off-voltage (V TGL ) is biased to −1.2 V during charge integration such that the TG channel is under the accumulation condition [3]. The nominal pixel supply is 2.8 V.…”

Total ionizing dose effects in pinned photodiode complementary metal-oxide-semiconductor transistor active pixel sensor

“…When V OFF is set to be at negative bias, the TG is accumulated with holes which recombine with dark electrons generated from interface defects 104207-2 and fill the traps caused by γ -irradiation around the TG. [11] If the dark current generated in the TG is suppressed by using a negative bias, the remaining dark current mainly comes from STI.…”

MOS-based model of four-transistor CMOS image sensor pixels for photoelectric simulation

“…As a result, several refined device designs have been developed. [15,16] For the PPD structure and its characterization, the relationship between the channel barrier height and FWC of the PPD during TG shutdown has been established. [12] The FWC qualitative analysis model of PPD uses the abstract pinned voltage model to fit the temperature and the concept of PPD capacitance.…”