Neighbor-A-Posteriori Information Assisted Cell-State Adaptive Detector for NAND Flash Memory

Peng, Zishuai; He, Ruiquan; Han, Guangjie; Cai, Guofa; Fang, Yi

doi:10.1109/lcomm.2019.2936342

Cited by 4 publications

(1 citation statement)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Thanks to these two key technologies: (1) continued scaling down process technology and (2) multilevel (e.g., MLC, TLC) cell data coding, the storage density of a NAND flash memory has been significantly increased over previous decades [1]. However, these two key technologies bring about a challenge in that the data stored in NAND flash memory may suffer from low reliability [2][3][4]. Furthermore, there are two major sources of noise in flash memory: cell-to-cell interference (CCI) and retention noise.…”

Section: Introductionmentioning

confidence: 99%

Artificial Neural Network Assisted Error Correction for MLC NAND Flash Memory

Xiong

et al. 2021

Micromachines

Self Cite

View full text Add to dashboard Cite

The multilevel per cell technology and continued scaling down process technology significantly improves the storage density of NAND flash memory but also brings about a challenge in that data reliability degrades due to the serious noise. To ensure the data reliability, many noise mitigation technologies have been proposed. However, they only mitigate one of the noises of the NAND flash memory channel. In this paper, we consider all the main noises and present a novel neural network-assisted error correction (ANNAEC) scheme to increase the reliability of multi-level cell (MLC) NAND flash memory. To avoid using retention time as an input parameter of the neural network, we propose a relative log-likelihood ratio (LLR) to estimate the actual LLR. Then, we transform the bit detection into a clustering problem and propose to employ a neural network to learn the error characteristics of the NAND flash memory channel. Therefore, the trained neural network has optimized performances of bit error detection. Simulation results show that our proposed scheme can significantly improve the performance of the bit error detection and increase the endurance of NAND flash memory.

show abstract