Shaving Retries with Sentinels for Fast Read over High-Density 3D Flash

Li, Qiao; Ye, Min; Cui, Yufei; Shi, Liang; Li, Xiaoqiang; Kuo, Tei-Wei

doi:10.1109/micro50266.2020.00048

Cited by 30 publications

(7 citation statements)

References 30 publications

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“…A concurrent study [56] with ours proposes a new V OPT prediction technique to reduce the number of retry steps. The key idea is to store predefined bit patterns in a set of spare cells in each page, called Sentinel cells, so as to accurately estimate the page's current error characteristics (and V OPT ) based on errors incurred in the predefined bit patterns.…”

Section: Related Workmentioning

confidence: 99%

“…Doing so allows the SSD controller to try near-optimal V REF values right after the first regular page read, which significantly reduces the average number of read-retry steps (from 6.6 to 1.2). Both of our proposed techniques, PR 2 and AR 2 , can complement the Sentinel-based approach [56] as well as other read-retry mitigation techniques [12, 13, 64-66, 77, 84] that aim to reduce the number of retry steps. First, once the SSD firmware accurately identifies the optimal V REF values using the Sentinel cells, it is possible to reduce the latency of the following retry step(s) using AR 2 , i.e., applying reduced read-timing parameters.…”

Section: Related Workmentioning

confidence: 99%

“…First, once the SSD firmware accurately identifies the optimal V REF values using the Sentinel cells, it is possible to reduce the latency of the following retry step(s) using AR 2 , i.e., applying reduced read-timing parameters. Second, PR 2 reduces the latency of a read-retry operation when the Sentinel-based V OPT prediction fails (as shown in [56], the Sentinel-based approach cannot completely avoid multiple retry steps), by speculatively issuing a new retry step. Full Utilization of Reliability Margin in Memory Devices.…”

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

Reducing solid-state drive read latency by optimizing read-retry

Park

Kim

Chun

et al. 2021

Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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3D NAND flash memory with advanced multi-level cell techniques provides high storage density, but suffers from significant performance degradation due to a large number of read-retry operations. Although the read-retry mechanism is essential to ensuring the reliability of modern NAND flash memory, it can significantly increase the read latency of an SSD by introducing multiple retry steps that read the target page again with adjusted read-reference voltage values. Through a detailed analysis of the read mechanism and rigorous characterization of 160 real 3D NAND flash memory chips, we find new opportunities to reduce the read-retry latency by exploiting two advanced features widely adopted in modern NAND flash-based SSDs: 1) the CACHE READ command and 2) strong ECC engine. First, we can reduce the read-retry latency using the advanced CACHE READ command that allows a NAND flash chip to perform consecutive reads in a pipelined manner. Second, there exists a large ECC-capability margin in the final retry step that can be used for reducing the chip-level read latency. Based on our new findings, we develop two new techniques that effectively reduce the read-retry latency: 1) Pipelined Read-Retry (PR 2 ) and 2) Adaptive Read-Retry (AR 2 ). PR 2 reduces the latency of a read-retry operation by pipelining consecutive retry steps using the CACHE READ command. AR 2 shortens the latency of each retry step by dynamically reducing the chip-level read latency depending on the current operating conditions that determine the ECC-capability margin. Our evaluation using twelve real-world workloads shows that our proposal improves SSD response time by up to 31.5% (17% on average) over a state-of-the-art baseline with only small changes to the SSD controller. CCS CONCEPTS• Hardware → External storage.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Reducing solid-state drive read latency by optimizing read-retry

Park

Kim

Chun

et al. 2021

Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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“…According to existing work, we know that higher voltages suffer more from retention errors [4,21]. This is because higher voltage states have more charge, and thus, the leakage speed is higher, which leads to more charge leakage.…”

Section: Finding 4: the Temperature Affects The Rber Variations Among Read Voltages As Well As Pagesmentioning

confidence: 99%

“…High-density solid-state drives (SSDs) are now widely used in data centers because of their performance and cost advantages. At the same time, the reliability of SSDs and their data endurance over the years are always of great concern [6,21,23,24]. The raw bit error rate (RBER) of SSDs' 3D NAND flash-memory chips is dominated by retention errors [4,5,32], which are caused by the charge leakage of flash cells over retention time.…”

Section: Introductionmentioning

confidence: 99%

How the common retention acceleration method of 3D NAND flash memory goes wrong?

Kuo

2021

Proceedings of the 13th ACM Workshop on Hot Topics in Storage and File Systems

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The reliability of solid-state drives (SSDs) has become increasingly important as SSDs are now widely applied in data centers. Retention error is a major source of impact on the reliability of SSDs. Even though the common practice in understanding the retention errors of an SSD is done by high-temperature baking processes, their characterization accuracy is not yet rigidly reviewed. In this paper, we first present how the common retention acceleration method goes wrong. Through a one-year study of 3D flash error behaviors, we found that the retention errors through baking with high temperatures have very different characteristics from the real long-retention errors. These differences come from the inherent structure and the materials of 3D NAND flash. Several findings regarding the retention errors characterized through baking are presented, followed by the analysis of the error behaviors. Finally, the retention errors of one year on 3D flash memory are provided with real data.

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Stop unnecessary refreshing: extending 3D NAND flash lifetime with ORBER

Gao

et al. 2022

CCF Trans. HPC

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Shaving Retries with Sentinels for Fast Read over High-Density 3D Flash

Cited by 30 publications

References 30 publications

Reducing solid-state drive read latency by optimizing read-retry

Reducing solid-state drive read latency by optimizing read-retry

How the common retention acceleration method of 3D NAND flash memory goes wrong?

Stop unnecessary refreshing: extending 3D NAND flash lifetime with ORBER

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