NEMsCAM: A novel CAM cell based on nano-electro-mechanical switch and CMOS for energy efficient TLBs

Abstract

Abstract-In this paper we propose a novel Content Addressable Memory (CAM) cell, NEMsCAM, based on both Nanoelectro-mechanical (NEM) switches and CMOS technologies. The memory component of the proposed CAM cell is designed with two complementary non-volatile NEM switches and located on top of the CMOS-based comparison component. As a use case for the NEMsCAM cell, we design first-level data and instruction Translation Lookaside Buffers (TLBs) with 16nm CMOS technology at 2GHz. The simulations show that the NEMsCAM TLB reduces the energy consumption per search operation (by 27%), write operation (by 41.9%) and standby mode (by 53.9%), and the area (by 40.5%) compared to a CMOSonly TLB with minimal performance overhead.

Energy-efficient address translation

“…Xue et al [53] proposed to speculatively perform address translation, based on the base-displacement address, by accessing a small L0 TLB early in the pipeline, so that the translation latency is not increased. Finally, Seyedi et al [47] proposed combining nano electro mechanical switches with CMOS technology for fully associative L1 TLBs.…”

Design and simulation of electrostatic NEMS logic gates

“…Pai and Tabib-Azar (2014) implemented the logic gates such as all or nothing gate (AND), any or all gate (OR) and XOR gates using microplasma with operating voltage in between 5 and 40 V with foot size of 50 × 5 μ m. Sinha et al (2012) reported the inverter, NAND and NOR mechanical logic gates using body-biased Aluminum Nitride (AlN) piezoelectric MEMS switches with operating swing voltages of ±2 V. Parsa et al (2013) implemented the 2 × 1 multiplexer using laterally actuated platinum-coated polysilicon NEM relays with operating gate pulse voltage of 10.75 V and beam voltage of 1 V. Rochus et al (2013) reported the design of inverters, NAND gate and ring oscillator based on NEMS relay which works similar to CMOS-based devices. Seyedi et al (2015) proposed content addressable memory component using NEM switches and CMOS transistors to realize the translation lookaside buffers with 16 nm technology works at 2 GHz for accessing data and instructions to complete the search operation within one clock cycle. Samaali et al (2015) reported mathematical modeling and finite element method solution for electrostatic-based single pole double throw switch (SPDT) micro switch used in a wireless sensor.…”

Design and simulation of electro-thermal compliant MEMS logic gates

“…Pai and Tabib-Azar (2014) implemented the logic gates such as AND, OR and exclusive or gate (XOR) gates using microplasma with operating voltage in between 5 and 40 V with foot size of 50 m m  5 m m. Sinha et al (2012) illustrated the inverter, NAND and NOR mechanical logic gates using body-biased AlN piezoelectric MEMS switches with operating swing voltages of 62 V. Parsa et al (2013) implemented the 2x1 multiplexer using laterally actuated platinum-coated polysilicon NEM relays with operating gate pulse voltage of 10.75 V and beam voltage of 1 V. Rochus et al (2013) reported the design of inverters, NAND gate and ring oscillator based on NEMS relay, which works similar to CMOS-based devices. Seyedi et al (2015) proposed content addressable memory component using NEM switches and CMOS transistors to realize the Translation Lookaside Buffers with 16 nm technology working at 2 GHz for accessing data and instructions to complete the search operation within one clock cycle. Proie et al (2011) reported the low-power Piezo MEMS-based 3-bit analog to digital converter (ADC), which operates without any additional electronic components.…”