NetFPGA SUME: Toward 100 Gbps as Research Commodity

Zilberman, Noa; Audzevich, Yury; Covington, G. Adam; Moore, Andrew W.

doi:10.1109/mm.2014.61

Cited by 239 publications

(166 citation statements)

References 11 publications

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“…Table 2 shows the resource requirement for an interconnect system with 16 ports. The NFV platform is implemented on the NetFPGA SUME board with Xilinx Virtex-7 690T FPGA chip [24]. The Network Master Pro MT1000A from Anritsu is used to generate and analyze the proposed NFV platform.…”

Section: Reconfiguration Processmentioning

confidence: 99%

Reconfigurable Network Stream Processing on Virtualized FPGA Resources

Chen

Mishra

Nunez-Yanez

et al. 2018

International Journal of Reconfigurable Computing

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The software defined network and network function virtualization are proposed to address the network ossification issue in current Internet infrastructure. Network functions and services are implemented as software applications to increase the programmability of network. However, involving general purpose processors in data plane restricts the bandwidth of network services. Therefore, to keep both the bandwidth and flexibility, a FPGA platform is suggested as a reconfigurable platform to deliver high bandwidth virtual network functions on data plane. In this paper, the FPGA resource has been virtualized by interconnecting partial reconfigurable regions to deliver high bandwidth reconfigurable processing on network streams. With the help of partial reconfiguration technology, network functions on our platform can be configured without affecting other functions on the same FPGA device. The on-chip interconnect system is further evaluated by comparing with existing network-on-chip system. A reconfiguration process is also proposed and demonstrated that it can be performed on our platform. The process can happen in the real time of network services and it is able to keep the original function working during the download of partial bitstream.

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Section: Reconfiguration Processmentioning

confidence: 99%

Reconfigurable Network Stream Processing on Virtualized FPGA Resources

Chen

Mishra

Nunez-Yanez

et al. 2018

International Journal of Reconfigurable Computing

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“…The resource requirement for a star topology NoC with 15 ports is shown in table II. The proposed NFV platform is implemented on the NetFPGA SUME board with Xilinx Virtex-7 690T FPGA chip [15]. The traffic is generated and analyzed by the Network Master Pro MT1000A from Anritsu [16].…”

Section: Experimental Demonstrationmentioning

confidence: 99%

Reconfigurable computing for network function virtualization: A protocol independent switch

Chen

Mishra

Zervas

2016

2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig)

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Abstract-Network function virtualization (NFV) aims to decouple software network applications from their hardware in order to reduce development and deployment costs for new services. To enable the deployment of diverse network services, a reconfigurable and high performance hardware platform can bring considerable benefits to NFV. In this paper, an FPGA-based platform is proposed to perform as a protocol reconfigurable NFV switch. Logic circuit of virtual network functions can be reconfigured at run time on the proposed platform. A reconfiguration process is also proposed to enable packet loss free switch-over between virtual network functions that delivers undisrupted service. The platform can be reconfigured between Layer 1 circuit switch and Layer 2 Ethernet packet switch. Once running as a packet switch, the platform can switch over from Layer 2 Ethernet switch to Layer 3 IP parser and even Layer 4 UDP parser. Performance of the implemented 2x2 switch at 10Gbps per port delivers a minimum latency of 300 nanoseconds (circuit switch) and maximum latency of 1 microsecond. Reconfiguration between IP and UDP parser without loss of data is also demonstrated.

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“…The NetFPGA SUME contains a core of Xilinx Virtex-7 FPGA device and five peripheral subsystems [5]. (1) High-speed serial interfaces subsystem which comprises thirty 13.1 GHZ GTH transceivers.…”

Section: Netfpga Sume Platformmentioning

confidence: 99%

The Development Status and Trend of NetFPGA

Cao

Zheng

Sun

2015

2015 International Conference on Network and Information Systems for Computers

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In recent years, with the rapid development of the Internet, ever increasing traffic and link-bandwidths presented serious challenges for computer network-related research such as high-speed algorithm and development of high-performance network equipment. Of course, increasing complication in hardware, firewall filtering and Encryption technology, makes programmability getting more and more attention in switches, routers and other network devices. This paper introduces the development process of NetFPGA, makes a comprehensive summary in the study of high performance network, and describes its advantages in high-speed, parallel and real-time. We present a brief introduction to our current work simultaneously. Finally, the paper points out the NetFPGA development direction and trends in future work.

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NetFPGA SUME: Toward 100 Gbps as Research Commodity

Cited by 239 publications

References 11 publications

Reconfigurable Network Stream Processing on Virtualized FPGA Resources

Reconfigurable Network Stream Processing on Virtualized FPGA Resources

Reconfigurable computing for network function virtualization: A protocol independent switch

The Development Status and Trend of NetFPGA

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