Network-on-Chip Firewall: Countering Defective and Malicious System-on-Chip Hardware

LeMay, Michael; Gunter, Carl A.

doi:10.1007/978-3-319-23165-5_19

Cited by 8 publications

(2 citation statements)

References 36 publications

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“…A representative work listing different type of threats is described in [11]. In our case, we are not concerned about physical attacks against the SoC, such as fault injection, sidechannel analysis, and chip rewriting.…”

Section: Threat Modelmentioning

confidence: 99%

Security in MPSoCs: A NoC Firewall and an Evaluation Framework

Grammatikakis

Papadimitriou

Petrakis

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In multiprocessor system-on-chip (MPSoC), a CPU can access physical resources, such as on-chip memory or I/O devices. Along with normal requests, malevolent ones, generated by malicious processes running in one or more CPUs, could occur. A protection mechanism is therefore required to prevent injection of malicious instructions or data across the system. We propose a self-contained Network-on-Chip (NoC) firewall at the network interface (NI) layer which, by checking the physical address against a set of rules, rejects untrusted CPU requests to the onchip memory, thus protecting all legitimate processes running in a multicore SoC. To sustain high performance, we implement the firewall in hardware, with rule-checking performed at segmentlevel based on deny rules. Furthermore, to evaluate its impact, we develop a novel framework on top of gem5 simulation environ- ment, coupling ARM technology and an instance of a commercial point-to-point interconnect from STMicroelectronics (STNoC). Simulation tests include scenarios in which legitimate and malicious processes, running in different CPUs, request access to shared memory. Our results indicate that a firewall implementation at the NI can have a positive effect on network performance by reducing both end-to-end network delay and power consumption.We also show that our coarse-grain firewall can prevent saturation of the on-chip network and performs better than fine-grain alternatives that perform rule checking at page-level. Simulation results are accompanied with field measurements performed on a Zedboard platform running Linux, whereas the NoC Firewall is implemented as a reconfigurable, memory-mapped device on top of AMBA AXI4 interconnect fabric.

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Section: Threat Modelmentioning

confidence: 99%

Security in MPSoCs: A NoC Firewall and an Evaluation Framework

Grammatikakis

Papadimitriou

Petrakis

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Our novelty lies in that we model an STNoC instanceits router, link and network interface -in a cycle-accurate way in the gem5 environment, by designing a 2-stage pipeline switch based on gem5's garnet fixed pipeline router. We also take into account the security mechanism as an integral part of the system, which appears to be an interesting research subject [9], [10]. Our results incorporate the overhead of the NoC firewall integrated with the network interface, presented in detail in [1], [2].…”

Section: Background and Motivationmentioning

confidence: 99%

Security Enhancements for building saturation-free, low-power NoC-based MPSoCs

Papadimitriou

Petrakis

Grammatikakis

et al. 2015

2015 IEEE Conference on Communications and Network Security (CNS)

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In the future almost every consumer electronics device will be connected to an ecosystem of third-party partners providing services such as payment, streaming content, and so on. Present work aims to expose the foundations of a secure environment by ensuring security on the edge devices. MPSoCs are widely used in edge devices due to their capability to execute multiple applications in single-chips. To achieve the targeted security level against physical adversaries, all communications between the MPSoC and its environment must be protected. In an MPSoC multiple processing elements such as CPUs send requests to different on-chip memories. Network-on-chip has been proposed for MPSoC design, aiming at increasing performance and reducing power compared to on-chip buses. Tailoring the NoC to application(s) takes place usually at designtime. The selection of NoC parameter values affects both performance and power, while configuring them unwisely can result in unnecessary area overhead and chip cost. In the present work we concentrate on a commercial interconnect called STNoC from STMicroelectronics. We keep the NoC parameters fixed, and we explore the effects from the variation of other parameters, such as the injection rate of the packets transmitted by the CPUs, and the activation/deactivation of a security mechanism integrated in the network interface of the NoC, for multiple traffic scenarios with each one representing different amount of legal and malicious requests, for different mappings, and for different node setups. Experimental results, reveal the conditions under which the NoC starts experiencing saturation phenomena.

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