Networked Power-Gated MRAMs for Memory-Based Computing

Abstract

Emerging non-volatile memory technologies open new perspectives for original computing architectures. In this paper, we propose a new type of flexible and energy-efficient architecture that relies on power-gated distributed Magnetoresistive Random-Access Memory (MRAM). The proposed architecture uses a Network-on-Chip (NoC) to interconnect MRAM-based clusters, processing elements, and managers. The NoC distributes application-specific commands to MRAM devices by means of packets. Configurable Network Interfaces (NI) allow to transform MRAM devices into smart units able to respond to incoming commands. In this context, three types of MRAM designs are proposed with different power-gating policies and granularities. A relevant database search engine case study is considered to illustrate the benefits of this proposed architecture. It is implemented with a Sparse-Neural-Network (SNN) approach and simulated in SystemC with different scenarios including hundreds of database queries. Hardware designs and accurate power estimations have been conducted. The obtained results demonstrate important power reduction with database hit rates of about 94%. Targeting 65nm technology, energy savings reach 87% when compared with an SRAM-based implementation. Moreover, a new asymmetric read/write MRAM type provides from 39% to 50% energy reduction with respect to the other fixed-granularity models. This results in a low-power, highly scalable and configurable implementation of memory-based computing.

Multi-Context TCAM-Based Selective Computing: Design Space Exploration for a Low-Power NN

“…The dynamic energy of one SCA operation is 80 pJ, while the static energy of SCA due to the leakage current of SRAM is 1.6 nJ. If the multiplication result is stored in MRAM (magnetoresistive RAM) [25] using MTJ devices instead of the SRAM, the non-volatile property can help to significantly reduce the leakage current of RAM. It is the next step of our work after this study that demonstrates the relevancy of the proposed SCA.…”

Run-Time Remapping Algorithm of Dataflow Actors on NoC-Based Heterogeneous MPSoCs

“…In order to cope with the command packet and associated notification packet concepts, the NIs implement some additional logic modules. The command packets were already proposed in [32] but only produced by the manager and for a specific application.…”